公开(公告)号：US09287252B2

公开(公告)日：2016-03-15

申请号：US13048411

申请日：2011-03-15

申请人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

发明人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

IPC分类号： H01L29/12 ,  H01L27/02

CPC分类号： H01L27/0207

摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

公开(公告)号：US20120235208A1

公开(公告)日：2012-09-20

申请号：US13048411

申请日：2011-03-15

申请人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

发明人： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

IPC分类号： H01L29/12 ,  H01L21/66

CPC分类号： H01L27/0207

摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

公开(公告)号：US20140008817A1

公开(公告)日：2014-01-09

申请号：US14024925

申请日：2013-09-12

申请人： Jaw-Juinn HORNG ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

发明人： Jaw-Juinn HORNG ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

摘要翻译： 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能通过半导体衬底传播的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US08850379B2

公开(公告)日：2014-09-30

申请号：US13352738

申请日：2012-01-18

申请人： Chien-Hung Chen ,  Yung-Chow Peng ,  Chung-Hui Chen ,  Chih Ming Yang

发明人： Chien-Hung Chen ,  Yung-Chow Peng ,  Chung-Hui Chen ,  Chih Ming Yang

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/12 ,  H01L27/0207 ,  H01L29/94

摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.

摘要翻译： 根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部 。 对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。 在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

公开(公告)号：US08546953B2

公开(公告)日：2013-10-01

申请号：US13324405

申请日：2011-12-13

申请人： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

发明人： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/04 ,  H01L21/44

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

摘要翻译： 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US20130346935A1

公开(公告)日：2013-12-26

申请号：US14012142

申请日：2013-08-28

申请人： Young-Chow PENG ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

发明人： Young-Chow PENG ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70

摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

公开(公告)号：US08549453B2

公开(公告)日：2013-10-01

申请号：US13362914

申请日：2012-01-31

申请人： Young-Chow Peng ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

发明人： Young-Chow Peng ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70

摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

摘要翻译： 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。

公开(公告)号：US20130198710A1

公开(公告)日：2013-08-01

申请号：US13362914

申请日：2012-01-31

申请人： Young-Chow Peng ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

发明人： Young-Chow Peng ,  Chung-Hui Chen ,  Chien-Hung Chen ,  Po-Zeng Kang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70

摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

摘要翻译： 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。

公开(公告)号：US08803320B2

公开(公告)日：2014-08-12

申请号：US13025763

申请日：2011-02-11

申请人： Chung-Hui Chen

发明人： Chung-Hui Chen

IPC分类号： H01L29/40

CPC分类号： H01L23/552 ,  H01L23/5225 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.

摘要翻译： 集成电路包括沿第一方向布线的信号线。 第一屏蔽图案基本上与信号线平行设置。 第一屏蔽图案具有具有第一尺寸的第一边缘和具有第二尺寸的第二边缘。 第一边缘基本上与信号线平行。 第一个维度大于第二个维度。 第二屏蔽图案基本上与信号线平行设置。 第二屏蔽图案具有具有第三尺寸的第三边缘和具有第四尺寸的第四边缘。 第三边缘基本上与信号线平行。 第三维度大于第四维度。 第四个边缘面向第二个边缘。 第一空间在第二和第四边之间。

公开(公告)号：US07973552B2

公开(公告)日：2011-07-05

申请号：US11950419

申请日：2007-12-04

申请人： Chung-Hui Chen

发明人： Chung-Hui Chen

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H01L27/0802 ,  H01L28/20

摘要： An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.

摘要翻译： 集成电路包括半导体衬底; 第一个节点; 第二个节点; 以及第一多个电阻器，每个在第一多个电阻器单元中。 第一多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。 集成电路还包括第二多个电阻器，每个电阻器在第二多个电阻器单元中。 第二多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。 第一多个电阻器由第一材料形成。 第二多个电阻器由不同于第一材料的第二材料形成。 集成电路还包括在第一和第二多个电阻器单元之一中的开关，并且串联连接到电阻器。