公开(公告)号：US20080299755A1

公开(公告)日：2008-12-04

申请号：US12123919

申请日：2008-05-20

申请人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

发明人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

IPC分类号： H01L21/283

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

摘要翻译： 非易失性存储器件的制造包括在半导体衬底上依次形成隧道氧化物层，第一导电层和氮化物层。 从隧道氧化物层，第一导电层和氮化物层形成堆叠图案，并且在与堆叠图案相邻的半导体衬底中形成沟槽。 进行氧化处理以在沟槽和第一导电层的侧壁上形成侧壁氧化物层。 将氯气引入经历氧化过程的堆叠图案的至少一部分中。 将Cl引入堆叠图案可以至少部分地固化在结构制造期间在其中引起的缺陷。

公开(公告)号：US20090203190A1

公开(公告)日：2009-08-13

申请号：US12320435

申请日：2009-01-26

申请人： Young-jin Noh ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek ,  Jin-hwa Heo

发明人： Young-jin Noh ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek ,  Jin-hwa Heo

IPC分类号： H01L21/762 ,  H01L21/30

CPC分类号： H01L21/76224

摘要： A method of forming a mask stack pattern and a method of manufacturing a flash memory device including an active area having rounded corners are provided. The method of manufacture including forming a mask stack pattern defining an active region, the mask stack pattern having a pad oxide layer formed on a semiconductor substrate, a silicon nitride layer formed on the pad oxide layer and a stack oxide layer formed on the silicon nitride layer, oxidizing a surface of the semiconductor substrate exposed by the mask stack pattern and lateral surfaces of the silicon nitride layer such that corners of the active region are rounded, etching the semiconductor substrate having an oxidized surface to form a trench in the semiconductor substrate, forming a device isolation oxide layer in the trench, removing the silicon nitride layer from the semiconductor substrate, and forming a gate electrode in a portion where the silicon nitride layer is removed.

摘要翻译： 提供一种形成掩模叠层图案的方法和制造包括具有圆角的有效区域的闪速存储器件的方法。 制造方法包括形成限定有源区的掩模叠层图案，掩模叠层图案具有形成在半导体衬底上的焊盘氧化层，形成在焊盘氧化物层上的氮化硅层和形成在氮化硅上的堆叠氧化物层 氧化由掩模堆叠图案和氮化硅层的侧表面暴露的半导体衬底的表面，使得有源区的角部变圆，蚀刻具有氧化表面的半导体衬底，以在半导体衬底中形成沟槽， 在沟槽中形成器件隔离氧化物层，从半导体衬底去除氮化硅层，并在除去氮化硅层的部分中形成栅电极。

公开(公告)号：US07799639B2

公开(公告)日：2010-09-21

申请号：US12123919

申请日：2008-05-20

申请人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

发明人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

摘要翻译： 非易失性存储器件的制造包括在半导体衬底上依次形成隧道氧化物层，第一导电层和氮化物层。 从隧道氧化物层，第一导电层和氮化物层形成堆叠图案，并且在与堆叠图案相邻的半导体衬底中形成沟槽。 执行氧化处理以在沟槽和第一导电层的侧壁上形成侧壁氧化物层。 将氯气引入经历氧化过程的堆叠图案的至少一部分中。 将Cl引入堆叠图案可以至少部分地固化在结构制造期间在其中引起的缺陷。

公开(公告)号：US20090134450A1

公开(公告)日：2009-05-28

申请号：US12153686

申请日：2008-05-22

申请人： Chul-sung Kim ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Young-Jin Noh

发明人： Chul-sung Kim ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Young-Jin Noh

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881

摘要： Provided is a tunneling insulating layer, a flash memory device including the same that increases a program/erase operation speed of the flash memory device and has improved data retention in order to increase reliability of the flash memory device, a memory card and system including the flash memory device, and methods of manufacturing the same. A tunneling insulating layer may include a first region and a second region on the first region, wherein the first region has a first nitrogen atomic percent, the second region has a second nitrogen atomic percent, and the second nitrogen atomic percent is less than the first nitrogen atomic percent. The flash memory device according to example embodiments may include a substrate including source and drain regions and a channel region between the source and drain regions, the tunneling insulating layer on the channel region, a charge storage layer on the tunneling insulating layer, a blocking insulation layer on the charge storage layer, and a gate electrode on the blocking insulation layer.

摘要翻译： 提供了一种隧道绝缘层，包括其的闪速存储器件，其提高闪速存储器件的编程/擦除操作速度，并且具有改进的数据保持以便提高闪存器件的可靠性，存储卡和系统包括 闪存装置及其制造方法。 隧道绝缘层可以包括在第一区域上的第一区域和第二区域，其中第一区域具有第一氮原子百分比，第二区域具有第二氮原子百分比，第二氮原子百分比小于第一区域的第一区域 氮原子百分比。 根据示例性实施例的闪速存储器件可以包括：衬底，其包括源极和漏极区域以及在源极和漏极区域之间的沟道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的电荷存储层，阻挡绝缘层 电荷存储层上的栅极电极和阻挡绝缘层上的栅电极。

公开(公告)号：US07893482B2

公开(公告)日：2011-02-22

申请号：US12428078

申请日：2009-04-22

申请人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

发明人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.

摘要翻译： 半导体器件包括具有表面的半导体衬底，从半导体衬底的表面突出的掩埋隔离区域和在隔离区域之间的半导体衬底的表面上的第一绝缘层，并且包括氟，氮和/或重的 氢杂质。 浮置电极位于第一绝缘层上，第二绝缘层位于浮置电极和隔离区上，而控制栅极位于第二绝缘层上。 还公开了形成半导体器件的相关方法。

公开(公告)号：US20080073693A1

公开(公告)日：2008-03-27

申请号：US11776297

申请日：2007-07-11

申请人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

发明人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.

摘要翻译： 半导体器件包括具有表面的半导体衬底，从半导体衬底的表面突出的掩埋隔离区域和在隔离区域之间的半导体衬底的表面上的第一绝缘层，并且包括氟，氮和/或重的 氢杂质。 浮置电极位于第一绝缘层上，第二绝缘层位于浮置电极和隔离区上，而控制栅极位于第二绝缘层上。 还公开了形成半导体器件的相关方法。

公开(公告)号：US07537993B2

公开(公告)日：2009-05-26

申请号：US11776297

申请日：2007-07-11

申请人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

发明人： Chul-sung Kim ,  Young-jin Noh ,  Bon-young Koo ,  Sung-kweon Baek

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.

摘要翻译： 半导体器件包括具有表面的半导体衬底，从半导体衬底的表面突出的掩埋隔离区域和在隔离区域之间的半导体衬底的表面上的第一绝缘层，并且包括氟，氮和/或重的 氢杂质。 浮置电极位于第一绝缘层上，第二绝缘层位于浮置电极和隔离区上，而控制栅极位于第二绝缘层上。 还公开了形成半导体器件的相关方法。

公开(公告)号：US09679977B2

公开(公告)日：2017-06-13

申请号：US14861794

申请日：2015-09-22

申请人： Jin-bum Kim ,  Chul-sung Kim ,  Deok-han Bae ,  Bon-young Koo

发明人： Jin-bum Kim ,  Chul-sung Kim ,  Deok-han Bae ,  Bon-young Koo

IPC分类号： H01L29/41 ,  H01L29/78 ,  H01L27/092 ,  H01L21/82 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8238

CPC分类号： H01L29/41783 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

公开(公告)号：US06890823B2

公开(公告)日：2005-05-10

申请号：US10426562

申请日：2003-04-30

申请人： Byeong-chan Lee ,  Si-young Choi ,  Chul-sung Kim ,  Jong-ryeol Yoo ,  Deok-hyung Lee

发明人： Byeong-chan Lee ,  Si-young Choi ,  Chul-sung Kim ,  Jong-ryeol Yoo ,  Deok-hyung Lee

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/6656

摘要： Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

摘要翻译： 公开了在栅电极的侧壁上形成热氧化层的方法。 特别地，可以通过在集成电路基板上形成栅电极并使用热氧化工艺在栅电极的侧壁上形成热氧化层，在栅电极的侧壁上形成热氧化物层。 在形成热氧化物层之后，可以在栅电极上形成硅化物层。

公开(公告)号：US07579249B2

公开(公告)日：2009-08-25

申请号：US11688554

申请日：2007-03-20

申请人： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

发明人： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

摘要翻译： 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。