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公开(公告)号：US06829127B1
公开(公告)日：2004-12-07
申请号：US10383133
申请日：2003-03-05
IPC分类号： H02H300
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L28/90 , H01L29/945
摘要： A capacitive electrode structure for use in an integrated circuit fabricated on a substrate comprises a first electrode formed by a diffusion region in the substrate, an insulating layer formed on the diffusion region, and a second electrode formed by a conductive layer deposited on said insulating layer. To increase the capacitance per chip area of the capacitive electrode structure, a plurality of recesses are formed in the first electrode on an upper surface thereof with a lower surface of the second electrode substantially following a contour of these recesses. In one embodiment, the capacitive electrode structure is employed for a capacitor formed between a control gate and a floating gate in an EEPROM cell. Capacitors in other types of integrated circuit can be likewise formed using the electrode structure of the present invention. Preferably, the recesses in the diffusion region are formed concurrently with oxide-filled isolation trenches in the substrate used to isolate adjacent circuit elements from each other.
摘要翻译： 用于制造在衬底上的集成电路中的电容电极结构包括由衬底中的扩散区形成的第一电极，形成在扩散区上的绝缘层，以及由沉积在所述绝缘层上的导电层形成的第二电极 。 为了增加电容电极结构的每个芯片面积的电容，在其上表面上的第一电极中形成多个凹槽，其中第二电极的下表面大致遵循这些凹槽的轮廓。 在一个实施例中，电容电极结构用于形成在EEPROM单元中的控制栅极和浮置栅极之间的电容器。 可以使用本发明的电极结构同样地形成其他类型的集成电路中的电容器。 优选地，扩散区域中的凹部与用于将相邻电路元件彼此隔离的衬底中的氧化物填充隔离沟槽同时形成。
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公开(公告)号：US07045427B2
公开(公告)日：2006-05-16
申请号：US10830359
申请日：2004-04-22
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842
摘要： A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.
摘要翻译： 一种用于在半导体衬底上制造晶体管的方法包括：在多晶硅区域的中心区域的多晶硅掺杂水平下改变扩散区域的第一和第二边缘附近的多晶硅掺杂水平。
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3.发明授权
公开(公告)号：US5010029A
公开(公告)日：1991-04-23
申请号：US313984
申请日：1989-02-22
IPC分类号： H01L21/336 , H01L21/66 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/78
摘要： A process for fabricating field effect transistors with lightly doped drain (LDD) regions having a selected width includes a method of optically detecting the width of spacers used to mask the LDD regions during the source and drain implant and a method of electrically determining (confirming) the width of the LDD regions. In the optical method, reference structures are formed concurrently with the fabrication of the gates for FETs, a spacer material is formed on the substrate, the gates and the reference structures, the spacer material is etched away and the width of the spacers is optically detected by aligning the edges of spacers extending from two reference structures separated by a known distance. In the electrical method, the width is determined by defining a test area with known dimension, forming both N.sup.+ and N.sup.- regions in the test area, measuring the resistance across the test area, calculating the resistance of the N.sup.+ and N.sup.- regions, and calculating the width of the N.sup.- region from the resistance of the N.sup.- region.
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4.发明授权Non-selective implantation process for forming contact regions in integrated circuits 失效用于在集成电路中形成接触区域的非选择性注入工艺
公开(公告)号：US4709467A
公开(公告)日：1987-12-01
申请号：US839756
申请日：1986-03-13
申请人： Yow-Juang (Bill) Liu
发明人： Yow-Juang (Bill) Liu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/74 , H01L29/45 , H01L21/265
CPC分类号： H01L21/743 , H01L21/28512 , H01L29/456
摘要： An integrated circuit fabrication technique for a maskless method of forming contact regions in integrated circuits is disclosed. By carefully controlling implant dosages, ions of one conductivity type can be introduced into substrate regions having the same conductivity type to form enhanced characteristic contact regions without affecting the operational characteristics of substrate regions having the opposite conductivity type. The resulting cross-sectional profile of the regions of the one conductivity type allows fabrication overlap tolerances to be reduced and improves the contact regions' imperviousness to the spiking phenomenon.
摘要翻译： 公开了一种用于在集成电路中形成接触区域的无掩模方法的集成电路制造技术。 通过仔细地控制植入剂量，可以将一种导电类型的离子引入具有相同导电类型的衬底区域中，以形成增强的特征接触区域，而不影响具有相反导电类型的衬底区域的操作特性。 所得到的一种导电类型的区域的横截面轮廓允许制造重叠公差降低，并改善接触区域对尖峰现象的不透性。
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公开(公告)号：US07279952B1
公开(公告)日：2007-10-09
申请号：US11223270
申请日：2005-09-09
IPC分类号： H03K5/08
CPC分类号： H03K5/08 , H03K19/018507
摘要： A voltage converter includes a first N-channel MOSFET transistor, an inverter, a plurality of serially-connected diodes and a second N-channel MOSFET transistor. The inverter is coupled to the gate of the first N-channel MOSFET transistor to turn on/off the voltage converter. The anode of the diodes is coupled to the source of the first N-channel MOSFET transistor and the cathode of the diodes are coupled to the drain of the second N-channel MOSFET transistor. Since the source of the second N-channel MOSFET transistor is ground, the voltage clamped at the source of the first N-channel MOSFET transistor is not higher than 3.4V when a high voltage applied to the gate of the second N-channel MOSFET transistor turns it on.
摘要翻译： 电压转换器包括第一N沟道MOSFET晶体管，反相器，多个串联二极管和第二N沟道MOSFET晶体管。 反相器耦合到第一N沟道MOSFET晶体管的栅极以导通/关断电压转换器。 二极管的阳极耦合到第一N沟道MOSFET晶体管的源极，二极管的阴极耦合到第二N沟道MOSFET晶体管的漏极。 由于第二N沟道MOSFET晶体管的源极被接地，所以当施加到第二N沟道MOSFET晶体管的栅极的高电压时，钳位在第一N沟道MOSFET晶体管的源极处的电压不高于3.4V 打开它。
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6.发明授权Methods for optimizing programmable logic device performance by reducing congestion 有权通过减少拥塞来优化可编程逻辑器件性能的方法公开(公告)号：US07210115B1
公开(公告)日：2007-04-24
申请号：US10884612
申请日：2004-07-02
申请人： Irfan Rahim , Yow-Juang (Bill) Liu
发明人： Irfan Rahim , Yow-Juang (Bill) Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5036
摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an optimized implementation. A logic circuit for a programmable logic device can be analyzed by taking into account the effects of hotspots, power supply voltage drops, and signal congestion on device performance. By modeling the performance of transistors and other components using position-dependent and signal-dependent variables such as temperature, voltage, and capacitance, the effects of congestion on device performance can be characterized and an optimum implementation of the logic design in a programmable logic device can be obtained.
摘要翻译： 提供了设计和制造可编程逻辑器件的方法和设备。 可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。 逻辑设计系统可以用于根据优化的实现来产生可编程逻辑器件的配置数据。 可以通过考虑热点，电源电压降和信号拥塞对器件性能的影响来分析可编程逻辑器件的逻辑电路。 通过使用位置相关和信号相关变量（如温度，电压和电容）对晶体管和其他组件的性能进行建模，可以对设备性能拥塞的影响进行表征，并在可编程逻辑器件中实现逻辑设计 可以获得。
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公开(公告)号：US20060054974A1
公开(公告)日：2006-03-16
申请号：US10938102
申请日：2004-09-10
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/74
摘要： A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.
摘要翻译： 一种用于静电放电保护的半导体器件和方法。 半导体器件包括第一半导体可控整流器和第二半导体可控整流器。 第一半导体可控整流器包括第一半导体区域和第二半导体区域，并且第二半导体可控整流器包括第一半导体区域和第二半导体区域。 第一半导体区域与第一掺杂型相关联，并且第二半导体区域与不同于第一掺杂型的第二掺杂型相关联。 第二半导体区域直接位于绝缘层上。
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公开(公告)号：US07772591B1
公开(公告)日：2010-08-10
申请号：US11595329
申请日：2006-11-10
IPC分类号： H01L31/036
CPC分类号： H01L29/78 , H01L27/0203 , H01L27/112 , H01L27/11206
摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.
摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。
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9.发明授权Common geometry high voltage tolerant long channel and high speed short channel field effect transistors 失效普通几何高耐压长沟道和高速短沟道场效应晶体管
公开(公告)号：US5257095A
公开(公告)日：1993-10-26
申请号：US511853
申请日：1990-04-19
IPC分类号： H01L21/8236 , H01L29/78 , H01L29/10 , H01L29/68
CPC分类号： H01L21/8236 , H01L29/78
摘要： A field effect device transistor geometry and method of fabrication are described. The FET may be operated from a bias potential that forms an electrical field within the device exceeding a predetermined field strength. The device comprises a semiconductor substrate portion of a first conductivity type, said substrate portion having a major surface, and a region of a second conductivity type adjacent the major surface and adapted to receive the predetermined bias potential, the region including a subregion of like conductivity type and lesser conductivity, the subregion being positioned within the region such that the subregion receives at least that portion of the dipole electrical field including and exceeding the predetermined value.
摘要翻译： 描述了场效应器件晶体管的几何形状和制造方法。 FET可以从在器件内形成超过预定场强的电场的偏置电位来操作。 该器件包括第一导电类型的半导体衬底部分，所述衬底部分具有主表面，并且邻近主表面的第二导电类型的区域并且适于接收预定的偏置电位，所述区域包括类似电导率的子区域 类型和较小的导电性，该子区域位于该区域内，使得该子区域至少接收包括并超过预定值的偶极电场的至少该部分。
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公开(公告)号：US07470630B1
公开(公告)日：2008-12-30
申请号：US11107639
申请日：2005-04-14
申请人： Shuxian Chen , Yow-Juang (Bill) Liu
发明人： Shuxian Chen , Yow-Juang (Bill) Liu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L21/76816 , H01L23/522 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than the interconnect metal lines. To form this structure, first and second pluralities of trenches are formed in the dielectric layer. At least one of the second plurality of trenches is shallower than the first plurality of trenches. The first and second pluralities of trenches are filled with a conductive layer and then planarized.
摘要翻译： 集成电路包括半导体衬底和堆叠在衬底上的多个电介质层。 多个互连金属线和虚拟金属嵌入在电介质层中。 虚拟金属中的至少一个基本上比互连金属线更薄。 为了形成这种结构，在电介质层中形成第一和第二多个沟槽。 第二多个沟槽中的至少一个比第一多个沟槽浅。 第一和第二多个沟槽填充有导电层，然后平坦化。
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