公开(公告)号：US07772591B1

公开(公告)日：2010-08-10

申请号：US11595329

申请日：2006-11-10

申请人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang (Bill) Liu

发明人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang (Bill) Liu

IPC分类号： H01L31/036

CPC分类号： H01L29/78 ,  H01L27/0203 ,  H01L27/112 ,  H01L27/11206

摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。

公开(公告)号：US06897543B1

公开(公告)日：2005-05-24

申请号：US10646013

申请日：2003-08-22

申请人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

发明人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

IPC分类号： G11C17/16 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/112 ,  H01L27/12 ,  H01L29/00

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/983 ,  H01L2924/00

摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）反熔丝晶体管用作电可编程反熔丝。 在其未编程状态下，反熔丝晶体管截止并具有较高的电阻。 在编程期间，反熔丝晶体管导通，其熔化下面的硅并导致晶体管电阻的永久性降低。 感测电路监视反熔丝晶体管的电阻并相应地提供高或低输出信号。 反熔丝晶体管可以在编程期间通过在其衬底处相对于其源极升高电压而导通。 衬底可以通过电阻器接地。 可能通过使电流流过电阻器而使衬底偏置。 可以通过引起漏极 - 衬底结的雪崩击穿或通过产生连接到电阻器的外部齐纳二极管电路的齐纳击穿来使电流流过电阻器。

公开(公告)号：US07272067B1

公开(公告)日：2007-09-18

申请号：US11060925

申请日：2005-02-18

申请人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

发明人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

IPC分类号： G11C17/18

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/983 ,  H01L2924/00

摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）反熔丝晶体管用作电可编程反熔丝。 在其未编程状态下，反熔丝晶体管截止并具有较高的电阻。 在编程期间，反熔丝晶体管导通，其熔化下面的硅并导致晶体管电阻的永久性降低。 感测电路监视反熔丝晶体管的电阻并相应地提供高或低输出信号。 反熔丝晶体管可以在编程期间通过在其衬底处相对于其源极升高电压而导通。 衬底可以通过电阻器接地。 可能通过使电流流过电阻器而使衬底偏置。 可以通过引起漏极 - 衬底结的雪崩击穿或通过产生连接到电阻器的外部齐纳二极管电路的齐纳击穿来使电流流过电阻器。

公开(公告)号：US07157782B1

公开(公告)日：2007-01-02

申请号：US10780427

申请日：2004-02-17

申请人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang Liu

发明人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang Liu

IPC分类号： H01L29/00 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L23/58

CPC分类号： H01L29/78 ,  H01L27/0203 ,  H01L27/112 ,  H01L27/11206

摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。

公开(公告)号：US5130266A

公开(公告)日：1992-07-14

申请号：US573814

申请日：1990-08-28

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  Y10S148/147

摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

摘要翻译： 描述了一种用于制造轻掺杂漏极MOSFET集成电路器件的方法，其克服了多晶硅栅极上难熔金属硅化物层的剥离问题。 通过不使用被认为是成功制造多晶硅栅极轻掺杂漏极MOS FET集成电路所必需的几个高热循环工艺步骤，已经简化了本发明的工艺。 这些步骤是（1）在多晶硅蚀刻步骤之后的热氧化，（2）在用于间隔物制备的二氧化硅层的覆盖沉积之后的致密化步骤，和（3）耐火金属硅化物层之后的氧化硅封盖 通过各向异性蚀刻形成间隔物。 结果是提供非剥离多晶硅栅极轻掺杂漏极MOS FET集成电路器件的工艺。

公开(公告)号：US5449644A

公开(公告)日：1995-09-12

申请号：US181298

申请日：1994-01-13

申请人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76802 ,  Y10S148/133

摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.

摘要翻译： 描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。 提供半导体衬底，其中衬底的表面具有不平坦的形貌。 在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。 玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。 将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。 光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。 暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。 剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

公开(公告)号：US06785109B1

公开(公告)日：2004-08-31

申请号：US09756501

申请日：2001-01-08

申请人： Cheng H. Huang ,  Chiakang Sung ,  John Costello

发明人： Cheng H. Huang ,  Chiakang Sung ,  John Costello

IPC分类号： H02H322

CPC分类号： H01L27/0251

摘要： A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.

摘要翻译： 提供了一种用于为具有多个电源和/或接地总线的集成电路器件提供ESD保护的技术。 该技术涉及使用能够处理正和负ESD脉冲的钳位装置，以将设备内的每个电源总线，接地总线和I / O焊盘夹到相应的一个接地总线。 在不采取彻底的交叉钳位的情况下，这种布置为ESD事件期间在电源总线，接地总线和I / O焊盘的任何组合上施加的ESD脉冲提供放电路径。

公开(公告)号：US5989317A

公开(公告)日：1999-11-23

申请号：US856125

申请日：1997-05-14

申请人： Cheng H. Huang ,  Ray C. Wang ,  Teh Y. Liu ,  Cheng H. Chao

发明人： Cheng H. Huang ,  Ray C. Wang ,  Teh Y. Liu ,  Cheng H. Chao

IPC分类号： B01D19/00

CPC分类号： B01D19/0068

摘要： The present invention discloses a closed-loop method for recovering a process liquid and eliminating trapped air contained in the process liquid by utilizing a manual pump having generally a bellow construction for transporting the process liquid that contains trapped air back into a liquid reservoir for venting the trapped air.

摘要翻译： 本发明公开了一种闭环方法，用于回收工艺液体并通过利用通常具有波纹管结构的手动泵来除去包含在处理液体中的被捕获的空气，所述手动泵将包含被捕获的空气的处理液输回到液体储存器中， 被困空气

公开(公告)号：US5554566A

公开(公告)日：1996-09-10

申请号：US301537

申请日：1994-09-06

申请人： Water Lur ,  Cheng H. Huang

发明人： Water Lur ,  Cheng H. Huang

IPC分类号： H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76889 ,  H01L21/28061

摘要： A method for forming MOSFET devices, with an improved polycide gate has been accomplished. The polycide structure, made with metal silicide on polysilicon has a reduced rate of adhesion loss or peeling of the metal silicide from the underlying polysilicon, due to the unique surface of the polysilicon. The desired surface of the polysilicon, that will reduce the peeling phenomena, is a wavy or undulated surface. This is accomplished by either depositing the polysilicon at conditions that result in a hemi-spherical grained surface, or obtaining a similar wavy or undulated surface by treating smooth polysilicon in either phosphoric acid or by anodization in hydrofluoric acid. The adhesion of the subsequent metal silicide to the wavy surface of the polysilicon is improved to a point where peeling of the metal silicide from the underlying polysilicon is eliminated.

摘要翻译： 已经实现了用于形成具有改进的多晶硅栅极的MOSFET器件的方法。 由于多晶硅的独特表面，由多晶硅上的金属硅化物制成的多晶硅结构具有降低的粘附损失率或金属硅化物从下面的多晶硅的剥离。 多晶硅的期望的表面，其将减少剥离现象，是波浪形或波浪形的表面。 这可以通过在导致半球形颗粒表面的条件下沉积多晶硅，或通过在磷酸中处理光滑多晶硅或通过在氢氟酸中阳极氧化获得类似的波浪或波浪表面来实现。 随后的金属硅化物对多晶硅的波浪表面的粘附性得到改善，从而消除了金属硅化物与下面的多晶硅的剥离。

公开(公告)号：US5457065A

公开(公告)日：1995-10-10

申请号：US355490

申请日：1994-12-14

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造堆叠存储电容器的方法。 叠层电容器与作为动态随机存取存储器（DRAM）单元的一部分的场效应晶体管（FET）一起使用，用于以电容器上的存储电荷的形式存储数据。 用于制造电容器的方法包括从具有鳍状结构的单个多晶硅层形成底部电极，然后使用第二多晶硅层和等离子体回蚀以产生第二自对准鳍状结构，其显着增加 电容器底部电极的表面积。 然后通过在底部电极上形成薄的电容器电介质层并沉积第三多晶硅层以形成顶部电极并且以显着增加的电容和经济的加工步骤完成电容器来完成电容器结构。