公开(公告)号：US4788655A

公开(公告)日：1988-11-29

申请号：US874700

申请日：1986-06-16

申请人： Yozo Nakayama ,  Masahito Kubo ,  Yuuichi Yawata

发明人： Yozo Nakayama ,  Masahito Kubo ,  Yuuichi Yawata

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/483 ,  G06F7/57 ,  G06F9/22 ,  G06F9/32

CPC分类号： G06F7/57 ,  G06F9/226 ,  G06F9/30094 ,  G06F7/49905

摘要： A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred. The system also includes a device for producing a new condition code from the plurality of detection signals and the condition code already stored in the storing device depending on a value of the condition control field and for setting the new condition code in the storing device.

摘要翻译： 用于由微程序控制并对二进制浮点数据进行操作的运算单元的条件代码产生系统产生具有多个位的条件码并描述二进制浮点数据的属性。 条件码产生系统包括：存储装置，用于存储条件码的每一位; 用于根据二进制浮点数据的预定位的值产生多个检测信号的装置。 该数据通过涉及数据传送的微指令传送到算术单元内的总线，其中微指令是构成微程序的多个微指令之一。 微指令包括由多个比特构成的条件控制字段，该多个比特具有取决于至少精度的值和被传送的二进制浮点数据的数据部分。 该系统还包括根据条件控制字段的值从已经存储在存储装置中的多个检测信号和条件代码产生新的条件代码的装置，并且用于在存储装置中设置新的条件代码。

公开(公告)号：US5301331A

公开(公告)日：1994-04-05

申请号：US776347

申请日：1991-11-19

申请人： Haruhiko Ueno ,  Yozo Nakayama

发明人： Haruhiko Ueno ,  Yozo Nakayama

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4812 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877

摘要： An interruption processing system enables a basic CPU resource using process to be executed asynchronously, enabling an interruption handler to be easily created. Interruption handling of the basic CPU resource using process interruption handler to be executed asynchronously enables corresponding interruption handler process is terminated for a CPU resource using process dependent interruption factor. The interruption processing system comprises a queuing unit for determining whether an instruction stored in an instruction buffer designates a synchronous process or an asynchronous process and for queuing the instruction when it is an asynchronous process. When more than one asynchronous process which has been queued is terminated unprocessed or with exceptions in the case where an interruption is generated in a synchronous processing unit or an asynchronous processing unit or an interruption from the outside of a CPU is detected, contents and termination methods of all asynchronous processes terminated unprocessed or with exceptions at the time of the generation of the interruption are displayed in order to resume the program prior to the generation of the interruption.

摘要翻译： PCT No.PCT / JP91 / 00370 Sec。 371日期：1991年11月19日 102（e）1991年11月19日PCT PCT 1991年3月19日PCT公布。 公开号WO91 / 14985 日期为1991年10月3日。中断处理系统使基本CPU资源使用过程能够异步执行，从而能够轻松创建中断处理程序。 使用异步执行的处理中断处理程序对基本CPU资源的中断处理使得使用与过程相关的中断因素的CPU资源终止对应的中断处理程序处理。 所述中断处理系统包括排队单元，用于确定存储在指令缓冲器中的指令是否指定同步进程或异步进程，并且当所述指令是异步进程时排队。 当在同步处理单元或异步处理单元中产生中断或者从CPU外部产生中断的情况下，排队等待的多个异步处理被终止，或异常处理时，内容和终止方法 显示终止未处理的所有异步进程或在产生中断时出现异常，以便在生成中断之前恢复程序。

公开(公告)号：US6038674A

公开(公告)日：2000-03-14

申请号：US352343

申请日：1999-07-13

申请人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura

发明人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0808

摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

摘要翻译： 多处理器，其中多个处理器经由系统总线连接。 多处理器包括每个具有至少一个处理器，主存储器，高速缓冲存储器，高速缓存控制单元，目录存储器和目录控制单元的处理器组。 目录控制单元包括无效命令发布单元，其向存储在高速缓存行中的目录存储器中的所有参考指定发出高速缓存行无效命令。 因此，可以通过减少从缓存存储器发出高速缓存无效命令的频率来缩短设备处理时间。

公开(公告)号：US6092173A

公开(公告)日：2000-07-18

申请号：US824871

申请日：1997-03-26

申请人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Yozo Nakayama ,  Jun Sakurai ,  Toshiyuki Muta ,  Takayuki Shimamura

发明人： Takatsugu Sasaki ,  Akira Kabemoto ,  Hirohide Sugahara ,  Junji Nishioka ,  Yozo Nakayama ,  Jun Sakurai ,  Toshiyuki Muta ,  Takayuki Shimamura

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0813 ,  G06F12/0808

摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

公开(公告)号：US5890217A

公开(公告)日：1999-03-30

申请号：US598243

申请日：1996-02-07

申请人： Akira Kabemoto ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura ,  Hirohide Sugahara ,  Junji Nishioka ,  Takatsugu Sasaki ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Hiroaki Ishihata ,  Takeshi Horie ,  Toshiyuki Shimizu

发明人： Akira Kabemoto ,  Naohiro Shibata ,  Toshiyuki Muta ,  Takayuki Shimamura ,  Hirohide Sugahara ,  Junji Nishioka ,  Takatsugu Sasaki ,  Satoshi Shinohara ,  Yozo Nakayama ,  Jun Sakurai ,  Hiroaki Ishihata ,  Takeshi Horie ,  Toshiyuki Shimizu

IPC分类号： G06F12/08 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F2212/2542

摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

摘要翻译： 多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。 处理器模块通过第二系统总线相互连接。 通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

公开(公告)号：US07383168B2

公开(公告)日：2008-06-03

申请号：US10337559

申请日：2003-01-06

申请人： Rajarshi Mukherjee ,  Toshiya Mima ,  Yozo Nakayama

发明人： Rajarshi Mukherjee ,  Toshiya Mima ,  Yozo Nakayama

IPC分类号： G06F9/45

CPC分类号： G01R31/31704

摘要： A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the states, and the test element is applied to a design-under-test. Data flow information, determined while applying the test element to the design-under-test, is store in a transaction database, and the data items read and modified by the data flow information are stored in a data database. At least one result is determined based on the application of the test element to the design-under-test.

摘要翻译： 描述了元件测试的方法和系统。 生成第一模块并具有至少一个关联状态。 基于第一模块生成第二模块。 第二个模块与测试元件相关联。 测试元件基于第二个模块和状态进行控制，并将测试元件应用于被测设计。 将测试元素应用于测试设计时确定的数据流信息存储在事务数据库中，由数据流信息读取和修改的数据项存储在数据数据库中。 至少一个结果是根据测试元件在测试设计中的应用来确定的。