公开(公告)号：US20100252530A1

公开(公告)日：2010-10-07

申请号：US12721903

申请日：2010-03-11

Applicant: Robert Jeffrey Durante ,  Seung Jin Lee ,  Thomas Peter Tufano ,  Young Chul Park ,  Jun Woo Lee ,  Seung Yong Lee ,  Hyun Kyu Lee ,  Yu Jin Lee ,  Sang Hoon Jang

Inventor： Robert Jeffrey Durante ,  Seung Jin Lee ,  Thomas Peter Tufano ,  Young Chul Park ,  Jun Woo Lee ,  Seung Yong Lee ,  Hyun Kyu Lee ,  Yu Jin Lee ,  Sang Hoon Jang

IPC: C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C09K13/00

CPC classification number: C23F1/18 ,  C23F1/02 ,  C23F1/26 ,  C23F1/44 ,  H01L21/32134 ,  H05K3/067 ,  H05K3/388

Abstract: The present invention provides an etchant composition comprising A) high strength potassium monopersulfate providing from about 0.025% to about 0.8% by weight of active oxygen; B) from about 0.01% to about 30% by weight of the composition of B1) an organic acid, alkali metal salt of an organic acid, ammonium salt of an organic acid, or a homopolymer of an organic acid, or B2) a halogen or nitrate salt of phosphonium, tetrazolium, or benzolium, or B3) a mixture of component B1) and B2); and C) from about 0% to about 97.49% by weight of the composition of water; and a method of etching a substrate using said composition.

Abstract translation: 本发明提供一种蚀刻剂组合物，其包含A）高强度单硫酸钾，其提供约0.025重量％至约0.8重量％的活性氧; B）占组合物重量的约0.01％至约30％B1）有机酸，有机酸的碱金属盐，有机酸的铵盐或有机酸的均聚物，或B2）卤素 或鏻，四唑或苯并三唑的硝酸盐，或B3）组分B1）和B2的混合物）; 和C）占组合物水重量的约0％至约97.49％; 以及使用所述组合物蚀刻衬底的方法。

公开(公告)号：US20080023755A1

公开(公告)日：2008-01-31

申请号：US11819858

申请日：2007-06-29

Applicant: Yu Jin Lee

Inventor： Yu Jin Lee

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/4236 ,  H01L21/76232 ,  H01L21/763 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10876 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device is provided. In the method, a bulb type recess is formed on a semiconductor substrate in an active region. A gate insulating film is formed over the semiconductor substrate and on a surface of the recess. A first polysilicon layer is formed over the gate insulating film. A silicon-on-dielectric (“SOD”) barrier film is formed on the first polysilicon layer at a lower part of the recess. A second polysilicon layer is formed over the semiconductor substrate and filling the recess. Impurity ions are injected into the second polysilicon layer. An annealing process is performed on the semiconductor substrate. A metal layer and a gate hard mask layer is formed and patterned over the second polysilicon layer to form a gate including the SOD barrier film.

Abstract translation: 提供一种制造半导体器件的方法。 在该方法中，在活性区域中的半导体衬底上形成灯泡型凹部。 在半导体衬底上和凹部的表面上形成栅极绝缘膜。 在栅绝缘膜上形成第一多晶硅层。 在凹部的下部的第一多晶硅层上形成有硅上电介质（“SOD”）阻挡膜。 第二多晶硅层形成在半导体衬底上并填充凹槽。 杂质离子注入第二多晶硅层。 对半导体基板进行退火处理。 在第二多晶硅层上形成并图案化金属层和栅极硬掩模层，以形成包括SOD阻挡膜的栅极。

公开(公告)号：US07833898B2

公开(公告)日：2010-11-16

申请号：US12427819

申请日：2009-04-22

Applicant: Yu Jin Lee

Inventor： Yu Jin Lee

IPC: H01L21/4763

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1666

Abstract: Manufacturing a resistance RAM device includes the steps of forming an insulation layer on a semiconductor substrate having a bottom electrode contact; etching the insulation layer to define a hole exposing the bottom electrode contact; depositing sequentially a bottom electrode material layer and a TMO material layer selectively within the hole; depositing a top electrode material layer within the hole and on the insulation layer in such a way as to completely fill the hole in which the bottom electrode material layer and the TMO material layer are formed; removing partial thicknesses of the top electrode material layer and the insulation layer to form a stack pattern comprising a bottom electrode, a TMO, and a top electrode.

Abstract translation: 制造电阻RAM器件包括在具有底部电极接触的半导体衬底上形成绝缘层的步骤; 蚀刻绝缘层以限定暴露底部电极接触的孔; 在孔内顺序地沉积底电极材料层和TMO材料层; 在孔内和绝缘层上沉积顶部电极材料层，以完全填充其中形成底部电极材料层和TMO材料层的孔; 去除顶部电极材料层和绝缘层的部分厚度，以形成包括底部电极，TMO和顶部电极的堆叠图案。

公开(公告)号：US07566645B2

公开(公告)日：2009-07-28

申请号：US11819858

申请日：2007-06-29

Applicant: Yu Jin Lee

Inventor： Yu Jin Lee

IPC: H01L21/3205 ,  H01L29/76

CPC classification number: H01L29/4236 ,  H01L21/76232 ,  H01L21/763 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10876 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device is provided. In the method, a bulb type recess is formed on a semiconductor substrate in an active region. A gate insulating film is formed over the semiconductor substrate and on a surface of the recess. A first polysilicon layer is formed over the gate insulating film. A silicon-on-dielectric (“SOD”) barrier film is formed on the first polysilicon layer at a lower part of the recess. A second polysilicon layer is formed over the semiconductor substrate and filling the recess. Impurity ions are injected into the second polysilicon layer. An annealing process is performed on the semiconductor substrate. A metal layer and a gate hard mask layer is formed and patterned over the second polysilicon layer to form a gate including the SOD barrier film.

Abstract translation: 提供一种制造半导体器件的方法。 在该方法中，在活性区域中的半导体衬底上形成灯泡型凹部。 在半导体衬底上和凹部的表面上形成栅极绝缘膜。 在栅绝缘膜上形成第一多晶硅层。 在凹部的下部的第一多晶硅层上形成有硅上电介质（“SOD”）阻挡膜。 第二多晶硅层形成在半导体衬底上并填充凹槽。 杂质离子注入第二多晶硅层。 对半导体基板进行退火处理。 在第二多晶硅层上形成并图案化金属层和栅极硬掩模层，以形成包括SOD阻挡膜的栅极。