公开(公告)号：US08594605B2

公开(公告)日：2013-11-26

申请号：US13357664

申请日：2012-01-25

申请人： Yusaku Katsube ,  Kosuke Tsuiji ,  Yutaka Igarashi ,  Akio Yamamoto

发明人： Yusaku Katsube ,  Kosuke Tsuiji ,  Yutaka Igarashi ,  Akio Yamamoto

IPC分类号： H04B1/10 ,  H04K3/00

CPC分类号： H03H11/1252 ,  H03H11/1291 ,  H03H2210/012 ,  H03H2210/015 ,  H03H2210/025 ,  H03H2210/028

摘要： The present invention is directed to accurately set a frequency characteristic of a filter integrated in a semiconductor integrated circuit. A semiconductor integrated circuit includes a filter circuit, a cutoff frequency calibration circuit, and a Q-factor calibration circuit. The cutoff frequency calibration circuit adjusts cutoff frequency of the filter circuit to a desired value by adjusting capacitance components of the filter circuit. After adjustment of the cutoff frequency of the filter circuit by the cutoff frequency calibration circuit, the Q-factor calibration circuit adjusts the Q factor of the filter circuit to a desired value by adjusting a resistance component of the filter circuit.

摘要翻译： 本发明旨在精确地设定集成在半导体集成电路中的滤波器的频率特性。 半导体集成电路包括滤波电路，截止频率校准电路和Q因子校准电路。 截止频率校准电路通过调整滤波器电路的电容分量来将滤波器电路的截止频率调整到期望值。 在通过截止频率校准电路调节滤波电路的截止频率之后，Q因子校准电路通过调整滤波器电路的电阻分量来将滤波器电路的Q因子调节到期望值。

公开(公告)号：US08525584B2

公开(公告)日：2013-09-03

申请号：US13180303

申请日：2011-07-11

申请人： Yusaku Katsube ,  Yutaka Igarashi ,  Akio Yamamoto

发明人： Yusaku Katsube ,  Yutaka Igarashi ,  Akio Yamamoto

IPC分类号： H03K5/00

CPC分类号： H03H11/1291 ,  H03J2200/08 ,  H03J2200/10

摘要： The disclosed invention enables the cutoff frequency of a filter to be automatically adjusted to an arbitrary setting value within the adjustment range. An automatic cutoff frequency adjusting circuit includes a voltage/current converter circuit, a charge circuit, a discharge circuit, a digital capacitance having a plurality of electrostatic capacitances, a comparator for comparing a voltage inputted to the digital capacitance with a reference voltage, and a capacitance control circuit for controlling the digital capacitance. The time until the comparator detects that the voltage inputted to the digital capacitance is higher than the reference voltage after a reset signal has become a predetermined logic level is measured, and the digital capacitance is controlled by repeating, under a predetermined condition, processing for obtaining a next setting value of the digital capacitance, based on a measurement result, a target value of the digital capacitance, and the current value of the digital capacitance.

摘要翻译： 所公开的发明使得能够将滤波器的截止频率自动调整到调整范围内的任意设定值。 自动截止频率调节电路包括电压/电流转换器电路，充电电路，放电电路，具有多个静电电容的数字电容，用于将输入到数字电容的电压与参考电压进行比较的比较器，以及 用于控制数字电容的电容控制电路。 在比较器检测到在复位信号已经变为预定逻辑电平之后，比较器检测到输入到数字电容的电压高于参考电压的时间，并且通过在预定条件下重复以获得的处理来控制数字电容 基于测量结果，数字电容的目标值和数字电容的当前值的数字电容的下一个设定值。

公开(公告)号：US20070190961A1

公开(公告)日：2007-08-16

申请号：US11585996

申请日：2006-10-25

申请人： Yutaka Igarashi ,  Yusaku Katsube ,  Akio Yamamoto

发明人： Yutaka Igarashi ,  Yusaku Katsube ,  Akio Yamamoto

IPC分类号： H04B1/06 ,  H04B1/28

CPC分类号： H04B1/30

摘要： In a signal receiving circuit of a direct conversion system applied with a semiconductor integrated circuit for radio communication having a PLL requiring a clock signal, an LNA requiring low-noise receiving characteristics, and others, a variable coupling line is provided between clock signal buffers and at an input stage of the PLL, so that coupling between the variable coupling line and an input terminal of the LNA and coupling between the variable coupling line and a GND terminal of the LNA are made equal to each other at frequencies of higher harmonic waves of a clock signal. When the input terminal and the GND terminal of the LNA are excited at the same phase, since no output occurs at an output terminal of the LNA, an output of the LNA does not contain any higher harmonic wave of a clock signal.

摘要翻译： 在应用于具有需要时钟信号的PLL的无线电通信用半导体集成电路的直接转换系统的信号接收电路中，需要低噪声接收特性的LNA等，在时钟信号缓冲器和 在PLL的输入级，使得可变耦合线与LNA的输入端之间的耦合以及可变耦合线与LNA的GND端之间的耦合使得在高次谐波的频率处彼此相等 一个时钟信号。 当LNA的输入端子和GND端子在相同相位被激励时，由于在LNA的输出端子处没有输出，所以LNA的输出不包含时钟信号的任何高次谐波。

公开(公告)号：US07565120B2

公开(公告)日：2009-07-21

申请号：US11585996

申请日：2006-10-25

申请人： Yutaka Igarashi ,  Yusaku Katsube ,  Akio Yamamoto

发明人： Yutaka Igarashi ,  Yusaku Katsube ,  Akio Yamamoto

IPC分类号： H04B1/06

CPC分类号： H04B1/30

摘要： In a signal receiving circuit of a direct conversion system applied with a semiconductor integrated circuit for radio communication having a PLL requiring a clock signal, an LNA requiring low-noise receiving characteristics, and others, a variable coupling line is provided between clock signal buffers and at an input stage of the PLL, so that coupling between the variable coupling line and an input terminal of the LNA and coupling between the variable coupling line and a GND terminal of the LNA are made equal to each other at frequencies of higher harmonic waves of a clock signal. When the input terminal and the GND terminal of the LNA are excited at the same phase, since no output occurs at an output terminal of the LNA, an output of the LNA does not contain any higher harmonic wave of a clock signal.

摘要翻译： 在应用于具有需要时钟信号的PLL的无线电通信用半导体集成电路的直接转换系统的信号接收电路中，需要低噪声接收特性的LNA等，在时钟信号缓冲器和 在PLL的输入级，使得可变耦合线与LNA的输入端之间的耦合以及可变耦合线与LNA的GND端之间的耦合使得在高次谐波的频率处彼此相等 一个时钟信号。 当LNA的输入端子和GND端子在相同相位被激励时，由于在LNA的输出端子处没有输出，所以LNA的输出不包含时钟信号的任何高次谐波。

公开(公告)号：US08331895B2

公开(公告)日：2012-12-11

申请号：US12846618

申请日：2010-07-29

申请人： Yusaku Katsube ,  Akio Yamamoto

发明人： Yusaku Katsube ,  Akio Yamamoto

IPC分类号： H04B1/10

CPC分类号： H04B1/1018

摘要： A receiving circuit is provided for performing reception of a plurality of band signals and suppression of blockers that remain in the plurality of band signals being received and converted in frequency. The receiving circuit includes a first low-pass filter that has a first pole position to suppress blockers remaining in a received signal by the first pole position, and a second low-pass filter that has a second pole position to suppress blockers remaining in a signal that has passed through said first low-pass filter by the second pole position. A switch that switches on/off an input-output path including the filters so that the received signal passes through said first filter without passing through the second filter when receiving a first band signal, while the received signal passes through both filters when receiving a second band signal different from the first band signal.

摘要翻译： 提供接收电路，用于执行多个频带信号的接收和抑制在频率上接收和转换的多个频带信号中的阻塞。 接收电路包括第一低通滤波器，该第一低通滤波器具有第一极位置，以通过第一极位置来抑制接收信号中残留的阻滞剂;以及第二低通滤波器，其具有第二极位置以抑制信号中残留的阻滞剂 其通过所述第一低通滤波器通过第二极位置。 一种开关，其接通/关闭包括滤波器的输入 - 输出路径，使得当接收到第一频带信号时接收信号通过所述第一滤波器而不通过第二滤波器，同时当接收到的信号在接收到第二滤波器时通过两个滤波器 频带信号与第一频带信号不同。

公开(公告)号：US20090023411A1

公开(公告)日：2009-01-22

申请号：US11718101

申请日：2005-02-23

申请人： Yusaku Katsube ,  Akio Yamamoto

发明人： Yusaku Katsube ,  Akio Yamamoto

IPC分类号： H04B1/06 ,  H04B1/16

CPC分类号： H04B1/1018

摘要： The present invention is a receiving circuit used for a cellular phone that is reduced in size and can realize low power consumption. In a signal reception circuit that is used in a cellular phone that perform transmission and reception of a plurality of band wireless signals and includes a low-pass filter for removing blockers unnecessary for signal reception, the low-pass filter 104 is composed of a plurality of filters composed of a plurality of different circuit configurations and having a plurality of different pole positions, switching between a filter for blocker removal and a filter configuration with reduced sensitivity degradation is performed by combining a plurality of filters for each signal reception band, and by performing power-off of an unnecessary filter portion in the filter configuration, power consumption is reduced. By constituting a plurality of different filters using filters mutually complementing their characteristics, a redundant filter configuration can be avoided, so that the area thereof can be suppressed to necessity minimum, and cost can be reduced.

摘要翻译： 本发明是用于移动电话的接收电路，其尺寸减小并且可以实现低功耗。 在用于执行多个频带无线信号的发送和接收的蜂窝电话中使用的信号接收电路，并且包括用于去除不需要信号接收的阻塞器的低通滤波器，低通滤波器104由多个 由多个不同的电路结构构成并且具有多个不同的极位置的滤波器，通过组合用于每个信号接收频带的多个滤波器，并且通过 在滤波器结构中执行不需要的滤波器部分的断电，功耗降低。 通过使用与其特性相互补充的滤波器构成多个不同的滤波器，可以避免冗余滤波器构造，从而可以将其面积抑制到必要最小，并且可以降低成本。

公开(公告)号：US07813710B2

公开(公告)日：2010-10-12

申请号：US11718101

申请日：2005-02-23

申请人： Yusaku Katsube ,  Akio Yamamoto

发明人： Yusaku Katsube ,  Akio Yamamoto

IPC分类号： H04B1/10

CPC分类号： H04B1/1018

摘要： The present invention is a receiving circuit used for a cellular phone that is reduced in size and can realize low power consumption. In a signal reception circuit that is used in a cellular phone that perform transmission and reception of a plurality of band wireless signals and includes a low-pass filter for removing blockers unnecessary for signal reception, the low-pass filter 104 is composed of a plurality of filters composed of a plurality of different circuit configurations and having a plurality of different pole positions, switching between a filter for blocker removal and a filter configuration with reduced sensitivity degradation is performed by combining a plurality of filters for each signal reception band, and by performing power-off of an unnecessary filter portion in the filter configuration, power consumption is reduced. By constituting a plurality of different filters using filters mutually complementing their characteristics, a redundant filter configuration can be avoided, so that the area thereof can be suppressed to necessity minimum, and cost can be reduced.

摘要翻译： 本发明是用于移动电话的接收电路，其尺寸减小并且可以实现低功耗。 在用于执行多个频带无线信号的发送和接收的蜂窝电话中使用的信号接收电路，并且包括用于去除不需要信号接收的阻塞器的低通滤波器，低通滤波器104由多个 由多个不同的电路结构构成并且具有多个不同的极位置的滤波器，通过组合用于每个信号接收频带的多个滤波器，并且通过 在滤波器结构中执行不需要的滤波器部分的断电，功耗降低。 通过使用与其特性相互补充的滤波器构成多个不同的滤波器，可以避免冗余滤波器构造，从而可以将其面积抑制到必要最小，并且可以降低成本。

公开(公告)号：US20060181362A1

公开(公告)日：2006-08-17

申请号：US11280819

申请日：2005-11-17

申请人： Isao Ikuta ,  Akio Yamamoto ,  Yusaku Katsube ,  Toshiya Uozumi ,  Yasuyuki Kimura

发明人： Isao Ikuta ,  Akio Yamamoto ,  Yusaku Katsube ,  Toshiya Uozumi ,  Yasuyuki Kimura

IPC分类号： H03B5/08

CPC分类号： H03B5/1841 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253

摘要： There are provided a voltage-controlled oscillator and an RF-IC for W-CDMA, which are capable of ensuring a wide frequency range and improving oscillation stability. The voltage-controlled oscillator (RF-IC) includes: switching A and B inductors generating a magnetic interaction between resonant A and B inductors of a resonant circuit; and an A_NMOS, a B_NMOS, a C_NMOS, and D_NMOS as switch/load means having together a function of changing an inductance value by the magnetic interaction between the resonant A and B inductors and the switching A and B inductors and a function of serving as loads of the switching A and B inductors. The A_NMOS, the B_NMOS, the C_NMOS, and the D_NMOS are turned ON/OFF by a control signal so as to control the mutual induction, whereby the oscillation frequency is switched by changing the inductance value of the resonant circuit. Also, oscillation stability is improved by increasing the inductance value.

摘要翻译： 提供了一种用于W-CDMA的压控振荡器和RF-IC，其能够确保较宽的频率范围并提高振荡稳定性。 压控振荡器（RF-IC）包括：开关A和B电感器，其在谐振电路的谐振A和B电感器之间产生磁相互作用; 以及作为开关/负载的A_NMOS，B_NMOS，C_NMOS和D_NMOS一起具有通过谐振A和B电感器与开关A和B电感器之间的磁相互作用改变电感值的功能，以及用作 开关A和B电感的负载。 通过控制信号使A_NMOS，B_NMOS，C_NMOS和D_NMOS变为ON / OFF，从而控制互感，从而通过改变谐振电路的电感值来切换振荡频率。 此外，通过增加电感值来提高振荡稳定性。

公开(公告)号：US20080309413A1

公开(公告)日：2008-12-18

申请号：US12102321

申请日：2008-04-14

申请人： Yutaka Igarashi ,  Akio Yamamoto

发明人： Yutaka Igarashi ,  Akio Yamamoto

IPC分类号： H03F3/04

CPC分类号： H03G1/0088 ,  H03F1/22 ,  H03F3/19 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/366 ,  H03F2200/492 ,  H03F2203/7206

摘要： In a gain switching LNA including a first transistor, a first transistor group (for example, second to ninth transistors) and a second transistor group (for example, tenth to seventeenth transistors), a first resistor connected between an emitter of the tenth transistor and a collector of the first transistor and a second resistor connected to emitters of eleventh to seventeenth transistors and the collector of the first transistor and having a resistance one seventh as high as that of the first resistor are provided. In a high-gain mode, since isolation of the tenth to seventeenth transistors which are turned OFF and the first and second to ninth transistors is secured by the first resistor and the second resistor, there is no deterioration in the noise factor.

摘要翻译： 在包括第一晶体管，第一晶体管组（例如第二至第九晶体管）和第二晶体管组（例如，第十至第十七晶体管）的增益切换LNA中，连接在第十晶体管的发射极和 提供第一晶体管的集电极和连接到第十一至第十七晶体管的发射极和第一晶体管的集电极并且具有与第一电阻器的电阻高七分之一的电阻的第二电阻器。 在高增益模式中，由于通过第一电阻器和第二电阻器确保了截止的第十至第十七晶体管和第一和第二至第九晶体管的隔离，因此噪声系数不会降低。

公开(公告)号：US20070146044A1

公开(公告)日：2007-06-28

申请号：US11581776

申请日：2006-10-17

申请人： Yutaka Igarashi ,  Akio Yamamoto

发明人： Yutaka Igarashi ,  Akio Yamamoto

IPC分类号： G06F7/44

CPC分类号： H03D7/166 ,  H03B27/00 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0043

摘要： A quadrature mixer circuit and an RF communication semiconductor integrated circuit capable of suppressing variations in secondary distortion while reducing the current consumption are provided. In a quadrature mixer circuit, even if local signals different by 90 degrees inputted to the bases of I transistors and Q transistors have large amplitudes, interference is suppressed by I resistors, Q resistors, and capacitors. Also, since the capacitors are provided, changes in bias current values can be suppressed. Accordingly, variations in secondary distortion can be suppressed. Furthermore, the capacitors combine current outputs of a differential circuit formed of I transistors and the resistor and a differential circuit formed of Q transistors and the resistor. Therefore, current consumption can also be reduced.

摘要翻译： 提供了能够抑制二次变形的变化同时降低电流消耗的正交混频器电路和RF通信半导体集成电路。 在正交混频器电路中，即使输入到I晶体管和Q晶体管的基极的90度的本地信号具有很大的幅度，I电阻器，Q电阻器和电容器也会抑制干扰。 此外，由于提供了电容器，所以可以抑制偏置电流值的变化。 因此，可以抑制二次变形的变化。 此外，电容器组合由I晶体管和电阻器形成的差分电路的电流输出和由Q晶体管和电阻器形成的差分电路。 因此，电流消耗也可以降低。