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27 条记录 (耗时 0.022 秒)

    Scanner interface for the line adapters of a communication controller
    1.
    发明授权
    Scanner interface for the line adapters of a communication controller 失效
    扫描仪界面，用于通信控制器的线路适配器

    公开(公告)号：US5010548A

    公开(公告)日：1991-04-23

    申请号：US297730

    申请日：1989-01-17

    申请人： Yves Granger ,  Daniel Wind

    发明人： Yves Granger ,  Daniel Wind

    IPC分类号： G06F13/22 ,  G06F13/38

    CPC分类号： G06F13/225 ,  G06F13/385

    摘要： A line-adapter of a communications controller includes, for scanning the teleprocessing lines connected to it, cyclic scanning means FES exchanging information with the lines through a serial bidirectional link on which data and control informations are partitioned into frames and slots. Since both the FES and the serial link work with their own timings, an interface FESA is provided to adapt the FES scanning to the serial link structure. This FESA includes temporary storage means for storing on the one hand, data and control information transmitted from the LICs to the FES (10) through the inbound serial link, and on the other hand, data and control information transmitted from the FES to the LICs through the outbound serial link. The access of the FES, the outbound and inbound serial link to the storage means is time-shared and granted by an arbitration logic, according to the relative priorities of operation of said elements within the line-adapter of the communications controller.

    Multi-module switching system
    3.
    发明授权
    Multi-module switching system 有权
    多模块交换系统

    公开(公告)号：US07187685B2

    公开(公告)日：2007-03-06

    申请号：US10215812

    申请日：2002-08-08

    申请人： Daniel Wind

    发明人： Daniel Wind

    IPC分类号： G06F15/16 ,  H04J3/06

    CPC分类号： H04L49/15 ,  H04L49/103 ,  H04L49/25 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/45

    摘要： A multi-module switching system comprising at least two switching modules adapted for receiving data packets from at least one input adapter and transmitting the data packets to at least one output adapter, each of the switching modules including a shared buffer for buffering a portion of a data packet received from an input adapter and transmitting the portion to an output adapter. One of the switching modules is a master module receiving a portion of a data packet containing a packet header and sending control information contained therein serially to each other switching module as a slave module. Each slave module includes a delay computing structure adapted for computing a delay needed to transmit the control information from the master module to this slave module and a first storing structure adapted for storing a portion of a data packet transmitted from an input adapter to the slave module during the delay, before transmitting the portion to a respective shared buffer such that the portion of data packet is not received by the shared buffer before the slave module has received the control information from the master module.

    摘要翻译： 一种多模块交换系统，包括至少两个交换模块，适于从至少一个输入适配器接收数据分组，并将数据分组发送到至少一个输出适配器，每个交换模块包括一个共享缓冲器，用于缓冲一部分 从输入适配器接收的数据分组并将该部分发送到输出适配器。 其中一个交换模块是主模块，其接收包含分组报头的数据分组的一部分，并将包含在其中的控制信息串行地发送给彼此的切换模块作为从模块。 每个从模块包括适于计算从主模块向该从模块发送控制信息所需的延迟的延迟计算结构，以及适于将从输入适配器发送的数据分组的一部分存储到从模块的第一存储结构 在所述延迟期间，在将所述部分发送到相应的共享缓冲器之前，使得所述部分数据分组在所述从模块已经从所述主模块接收到所述控制信息之前未被所述共享缓冲器接收。

    Method and system for flexible network processor scheduler and data flow
    4.
    发明申请
    Method and system for flexible network processor scheduler and data flow 失效
    灵活的网络处理器调度器和数据流的方法和系统

    公开(公告)号：US20070011223A1

    公开(公告)日：2007-01-11

    申请号：US11133477

    申请日：2005-05-18

    申请人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    发明人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    IPC分类号： G06F15/16

    CPC分类号： H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

    摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

    摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

    HASH COLLISION REDUCTION SYSTEM
    8.
    发明申请
    HASH COLLISION REDUCTION SYSTEM 有权
    HASH碰撞减少系统

    公开(公告)号：US20130311492A1

    公开(公告)日：2013-11-21

    申请号：US13475990

    申请日：2012-05-20

    申请人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    发明人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30002 ,  G06F17/30949 ,  H04L9/00 ,  H04L9/3236 ,  H04L45/7453

    摘要： An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

    摘要翻译： 一种改进的计算机系统，其可以包括具有计算机处理器的控制器，所述控制器在与引入到控制器的新组件接口时减少插入时间和/或冲突。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑以在一个密钥改变时提供雪崩效应，这导致几乎一半的比特 改变多个表。

    Queue scheduling mechanism in a data packet transmission system
    9.
    发明授权
    Queue scheduling mechanism in a data packet transmission system 失效
    数据包传输系统中的队列调度机制

    公开(公告)号：US07382792B2

    公开(公告)日：2008-06-03

    申请号：US10065808

    申请日：2002-11-21

    申请人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Francois Le Mauf ,  Daniel Wind

    发明人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Francois Le Mauf ,  Daniel Wind

    IPC分类号： H04L12/28

    CPC分类号： H04L47/6215 ,  H04L47/2458 ,  H04L47/28 ,  H04L47/50 ,  H04L47/527 ,  H04L47/6285 ,  H04W28/14 ,  H04W72/1242

    摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.

    摘要翻译： 在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由 用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。 队列调度机制包括在每个分组周期提供定义要由队列调度器考虑的优先级的值N的信用设备，由队列调度器从对应于优先级N的队列设备读取数据分组，而不是 队列设备由普通优先级抢占算法确定。

    Hash collision reduction system
    10.
    发明授权
    Hash collision reduction system 有权
    哈希碰撞减少系统

    公开(公告)号：US08762399B2

    公开(公告)日：2014-06-24

    申请号：US13475990

    申请日：2012-05-20

    申请人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    发明人： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30002 ,  G06F17/30949 ,  H04L9/00 ,  H04L9/3236 ,  H04L45/7453

    摘要： An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

    摘要翻译： 一种改进的计算机系统，其可以包括具有计算机处理器的控制器，所述控制器在与引入到控制器的新组件接口时减少插入时间和/或冲突。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑以在一个密钥改变时提供雪崩效应，这导致几乎一半的比特 改变多个表。