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公开(公告)号：US6118782A
公开(公告)日：2000-09-12
申请号：US879829
申请日：1997-06-20
IPC分类号： H04L12/935 , H04L12/947 , H04Q11/04 , H04L12/28
CPC分类号： H04L49/30 , H04L49/25 , H04L49/256 , H04L49/3081 , H04Q11/0478
摘要： The present invention relates to an Asynchronous Transfer Mode (ATM) network, and in particular to a system and a method for a number of ATM devices to share the facilities provided by a single ATM switch port. An ATM switch has a number of switch ports which may receive and transmit the data comprising information and a routing identifier. A number of ATM devices are connected in series to each other in a device chain, and at the ends to the chain to a first ATM port. The devices are adapted to distinguish between the information and the routing identifier and may receive and transmit information through the chain, with a first or head device receiving data from the ATM port and the last device transmitting data to the ATM port. A control computer is connected to a second ATM port and may be programmed with the identities of the ATM devices and communicate through the first switch port with a device in the device chain. Each ATM device may be programmed with mapping instructions so that data subsequently received by the device may be correctly routed according to the routing identifier.
摘要翻译： 本发明涉及一种异步传输模式（ATM）网络，特别涉及用于共享由单个ATM交换机端口提供的设施的多个ATM设备的系统和方法。 ATM交换机具有多个交换机端口，其可以接收和发送包括信息的数据和路由标识符。 许多ATM设备在设备链中彼此串联连接，并且在链的末端连接到第一ATM端口。 这些设备适于区分信息和路由标识符，并且可以通过链路接收和发送信息，第一或头部设备从ATM端口接收数据，最后一个设备将数据发送到ATM端口。 控制计算机连接到第二ATM端口，并且可以用ATM设备的标识来编程，并且通过第一交换机端口与设备链中的设备进行通信。 每个ATM设备可以用映射指令进行编程，使得随后由设备接收的数据可以根据路由标识符被正确路由。
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2.发明授权Method and apparatus for switching, multicasting, multiplexing and demultiplexing an ATM cell 失效用于ATM信元的切换，组播，复用和解复用的方法和装置
公开(公告)号：US6108335A
公开(公告)日：2000-08-22
申请号：US693996
申请日：1996-08-08
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/3081 , H04Q11/0478 , H04L2012/5672
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I.gtoreq.1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O.gtoreq.1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 该交换机包括从ATM网络接收ATM信元的I个输入端口，其中I> / = 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 交换机还包括连接到存储器阵列的O输出端口，其中O> / = 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
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公开(公告)号：US5995511A
公开(公告)日：1999-11-30
申请号：US628206
申请日：1996-04-05
CPC分类号： H04L12/5601 , H04L49/107 , H04Q11/0478 , H04L2012/5679 , H04L2012/5681
摘要： A queue control system is disclosed for use in connection with the transfer of information, in the form of information transfer units, in a digital network. The network provides a plurality of service rate classes, based on, for example transmission rates for the various paths. The information buffer control subsystem includes a information transfer unit receiver, a information transfer unit buffer and a group controller. The information transfer unit receiver receives the information transfer units, and the buffer is provided to buffer the received information transfer units prior to transmission. The group controller controls the buffering of information transfer units received by the information transfer unit receiver in the buffer. In that operation, the group controller aggregates the information transfer units for each path in the buffer according to respective service rate classes, in particular aggregating the information transfer units for each path in a queue and further aggregating the queues for the paths associated with each service rate class in a queue. A transmission scheduler is also disclosed for use in transferring information, in the form of information transfer units, each associated with a path, in a digital network. The network provides a plurality of service rate classes, based on, for example, transmission rates for the various paths. The information transfer units for each path in a path queue, and the path queues for the paths associated with each service rate class are aggregated in a service rate queue. The transmission scheduler includes a information transfer unit selector for selecting from among the service rate queues, one path queue to provide a information transfer unit for transmission, and a information transfer unit transmitter for transmitting the information transfer unit provided by the selected path queue.
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公开(公告)号：US5892932A
公开(公告)日：1999-04-06
申请号：US561365
申请日：1995-11-21
申请人： Hyong S. Kim
发明人： Hyong S. Kim
CPC分类号： H04L49/30 , H04L49/105 , H04L49/107 , H04L49/15 , H04L49/3081 , H04L49/50
摘要： There is shown an apparatus for switching. The apparatus for switching comprises L switching modules which switch packets, where L.gtoreq.2 and is an integer. In an embodiment, each of the L switching modules switch packets independent of any other switching module such that there is distributed switching of packets across the L switching modules. The apparatus also comprises an interconnection module which is connected to each of the L switching modules. The interconnection module that provides a passive backplane provides connectivity between the L switching modules. In an embodiment, the interconnection module provides space and time multiplexed connectivity between the L switching modules. In an other embodiment, the interconnection module is expandable without a priori knowledge of a final number of switching modules. In yet another embodiment, the interconnection module is reprogrammable in regard to connectivity between the L switching modules. The present invention pertains to a method for creating a switching apparatus. The method comprises the steps of connecting a first and at least a second switching module to an interconnection module. Next, there is the step of programming the interconnection module to create a desired connectivity between the first and second switching modules to the interconnection module. Then, there is the step of transferring a packet through the interconnection module and first and second switching modules. Then, there is the step of connecting at least one additional switching module to the interconnection module. Next, there is the step of reprogramming the interconnection module to create a desired connectivity between the first, second and third switching modules to the interconnection module. The present invention pertains to a method of directing a packet.
摘要翻译： 示出了用于切换的装置。 用于切换的装置包括L个切换模块，其切换分组，其中L> / = 2并且是整数。 在一个实施例中，L个交换模块中的每个切换模块独立于任何其他交换模块交换分组，使得分组跨越L个交换模块进行分布式交换。 该装置还包括连接到每个L个开关模块的互连模块。 提供无源背板的互连模块提供了L个交换模块之间的连接。 在一个实施例中，互连模块在L个交换模块之间提供空间和时间复用的连接。 在另一个实施例中，互连模块是可扩展的，而没有最终数量的交换模块的先验知识。 在另一个实施例中，互连模块关于L个交换模块之间的连接可重新编程。 本发明涉及一种用于创建开关装置的方法。 该方法包括将第一和至少第二切换模块连接到互连模块的步骤。 接下来，存在对互连模块进行编程以在第一和第二交换模块之间建立到互连模块的期望连接的步骤。 然后，通过互连模块和第一和第二交换模块传送分组的步骤。 然后，将至少一个附加开关模块连接到互连模块的步骤。 接下来，存在重新编程互连模块以在第一，第二和第三交换模块之间建立到互连模块的期望连接的步骤。 本发明涉及一种引导分组的方法。
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公开(公告)号：US5541918A
公开(公告)日：1996-07-30
申请号：US381110
申请日：1995-01-31
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/108 , H04L49/3081 , H04Q11/0478 , H04L2012/5681
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I>1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O>1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 交换机包括从ATM网络接收ATM信元的I个输入端口，其中I> 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 该交换机还包括连接到存储器阵列的O个输出端口，其中O> 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
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6.发明授权Method and a scheduler for controlling when a server provides service with rate control to an entity 失效方法和调度器，用于控制服务器何时向实体提供速率控制
公开(公告)号：US5845115A
公开(公告)日：1998-12-01
申请号：US375624
申请日：1995-01-20
申请人： Jon C. R. Bennett
发明人： Jon C. R. Bennett
CPC分类号： G06F9/5027 , G06F9/4881 , G06F9/5038 , G06Q10/06 , H04L29/06 , G06F2209/506 , H04L67/42
摘要： A method for scheduling when a server provides service to entities. The method includes the steps of identifying when a first entity requests service from the server. Next there is the step of providing service to an entity, such as a first entity or a second entity, as a function of virtual time. A scheduler for controlling when a server provides service to entities. The scheduler comprises a memory having times which are a function of when entities request service from the server. The scheduler is also comprised of a virtual clock that keeps track of time. The scheduler is also comprised of a controller which causes an entity to receive service from the server as a function of virtual time. Rate can also be utilized.
摘要翻译： 一种用于在服务器向实体提供服务时进行调度的方法。 该方法包括以下步骤：识别第一实体何时从服务器请求服务。 接下来，作为虚拟时间的函数，向诸如第一实体或第二实体的实体提供服务的步骤。 用于控制服务器何时向实体提供服务的调度器。 调度器包括具有时间的存储器，其是实体从服务器请求服务的功能。 调度器还包括跟踪时间的虚拟时钟。 调度器还包括控制器，其使得实体作为虚拟时间的函数从服务器接收服务。 费率也可以利用。
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7.发明授权Method and a scheduler for controlling when a server provides service with rate control to an entity 失效方法和调度器，用于控制服务器何时向实体提供速率控制
公开(公告)号：US5828878A
公开(公告)日：1998-10-27
申请号：US476365
申请日：1995-06-07
申请人： Jon C. R. Bennett
发明人： Jon C. R. Bennett
CPC分类号： H04L29/06 , G06F9/4881 , G06F9/5027 , H04L67/42
摘要： A scheduler for controlling when N entities, where N is an integer greater than or equal to one, are operated upon by a server. The scheduler includes a starting time memory. The starting time memory has only arriving times which are greater than virtual time. The scheduler also includes a finishing time memory. The finishing time memory has finishing times of the N entities whose starting times are less than or equal to virtual time. Additionally, the scheduler includes a virtual clock that keeps track of virtual time so the arriving times and finishing times can be identified. Moreover, the scheduler is also comprised of a controller for choosing entities to be operated upon by the server from the finishing time memory. A method of scheduling when a server provides service to entities.
摘要翻译： 用于控制N个实体（其中N是大于或等于1的整数）的调度器由服务器进行操作。 调度器包括启动时间存储器。 起始时间存储器只有到达时间大于虚拟时间。 调度器还包括完成时间存储器。 完成时间存储器具有起始时间小于或等于虚拟时间的N个实体的完成时间。 此外，调度器包括跟踪虚拟时间的虚拟时钟，从而可以识别到达时间和完成时间。 此外，调度器还包括用于从完成时间存储器中选择要由服务器操作的实体的控制器。 一种在服务器向实体提供服务时进行调度的方法。
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公开(公告)号：US5689512A
公开(公告)日：1997-11-18
申请号：US577917
申请日：1995-12-21
CPC分类号： H04L49/309 , H04L12/4608 , H04L45/742 , H04L49/253 , H04L49/256 , H04L49/3009 , H04L49/3081 , H04Q11/0478 , H04L2012/5617 , H04L2012/5665 , H04L49/555 , Y10S370/905 , Y10S370/911
摘要： A communication network. The communication network has an ATM network portion. The communication network has an ATM cell interface in communication with the ATM network portion. The communication network also has a first general purpose computer connected to the ATM network portion and in communication with the ATM cell interface through the ATM network portion. The communication network has a second general purpose computer connected to the ATM network portion and in communication with the ATM cell interface through the ATM network portion. The first computer and second computer each execute instructions for applications other than communications between computers. The computers can communicate at 155 mb/s or 622 mb/s. The ATM cell interface can be connected to an Ethernet, or a Sonet OC-3 or an FDDI. There is a method for dispatching an ATM cell.
摘要翻译： 通讯网络 通信网络具有ATM网络部分。 通信网络具有与ATM网络部分通信的ATM信元接口。 通信网络还具有连接到ATM网络部分并且通过ATM网络部分与ATM信元接口通信的第一通用计算机。 通信网络具有连接到ATM网络部分并且通过ATM网络部分与ATM信元接口通信的第二通用计算机。 第一台计算机和第二台计算机每个都执行除计算机之间的通信以外的应用程序的 计算机可以155 mb / s或622 mb / s进行通信。 ATM信元接口可以连接到以太网或Sonet OC-3或FDDI。 有一种调度ATM信元的方法。
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公开(公告)号：US5323389A
公开(公告)日：1994-06-21
申请号：US930081
申请日：1992-08-14
CPC分类号： H04L49/309 , H04L12/4608 , H04L45/742 , H04L49/253 , H04L49/256 , H04L49/3009 , H04L49/3081 , H04Q11/0478 , H04L2012/5617 , H04L2012/5665 , H04L49/555 , Y10S370/905 , Y10S370/911
摘要： An ATM cell interface for dispatching an ATM cell comprising N input ports, where N.gtoreq.1 and is an integer. A table lookup mechanism directs a cell from an input port to any desired destination. The table lookup mechanism has entries which identify desired destination for corresponding cells. The number of possible entries in the table lookup mechanism is less than a total number of entries supported by the ATM cell header. The table lookup mechanism preferably includes a first table which produces a first signal based on the value of the VPI field and a second level table which produces a second signal based on the value of the VCI field. The first and second signals are used to route the cell from an input port to a desired destination. A method for dispatching an ATM cell comprising the steps of locating a table entry in a first level table corresponding to a value of a VPI field of the cell. Then there is the step of producing a first signal corresponding to the table entry. Next, there is the step of locating a connection entry in a second level table corresponding to a value of a VCI field of the cell and the first signal. Then there is the step of producing a second signal corresponding to the connection entry. Next there is the step of directing a cell to a desired destination corresponding to the second signal.
摘要翻译： 一个用于调度包含N个输入端口的ATM信元的ATM信元接口，其中N≥1并且是整数。 表查找机制将单元格从输入端口引导到任何所需的目标。 表查找机制具有识别相应单元的所需目的地的条目。 表查找机制中可能的条目数量少于ATM信元头部支持的条目总数。 表查找机构优选地包括基于VPI字段的值产生第一信号的第一表和基于VCI字段的值产生第二信号的第二电平表。 第一和第二信号用于将单元从输入端口路由到期望的目的地。 一种用于调度ATM信元的方法，包括以下步骤：在与所述小区的VPI字段的值对应的第一级表中定位表条目。 然后，产生对应于表条目的第一信号的步骤。 接下来，存在将对应于小区的VCI字段的值和第一信号的第二级表中的连接条目定位的步骤。 然后，产生对应于连接条目的第二信号的步骤。 接下来，存在将单元指向对应于第二信号的期望目的地的步骤。
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公开(公告)号：US20040213240A1
公开(公告)日：2004-10-28
申请号：US09740151
申请日：2000-12-18
申请人： FORE Systems, Inc.
发明人： Vikrant H. Desai
IPC分类号： H04L012/28
CPC分类号： H04L12/5601 , H04L49/108 , H04L2012/5627 , H04L2012/5649
摘要： An apparatus for transferring data on a network. The apparatus includes a switch comprising a primary component for switching the data through the switch. The apparatus includes a secondary component for switching the data through the switch if the primary component fails. The apparatus includes a mechanism for counting the data that has been received, transmitted or dropped by the switch without including any redundancy in the counting of the data due to the primary component and secondary component both able to switch data through the switch. A method for transferring ATM cells on a network. The method includes the steps of switching the ATM cells with an ATM switch of the ATM network having a primary component for switching the cells and a secondary component for switching the cells if the primary component fails. Then there is the step of counting the cells that have been received, transmitted or dropped by the switch without including any redundancy in the counting if the cells due to the primary component and secondary component both able to switch the cells through the switch.
摘要翻译： 一种用于在网络上传送数据的装置。 该装置包括开关，该开关包括用于通过开关切换数据的主要部件。 该设备包括用于在主要组件发生故障时通过交换机切换数据的辅助组件。 该装置包括用于对由交换机接收，发送或丢弃的数据进行计数的机构，而不包括由于主要组件和辅助组件能够切换数据而导致的数据计数中的任何冗余。 一种用于在网络上传送ATM信元的方法。 该方法包括以下步骤：ATM网络的ATM交换机切换ATM单元，其具有用于交换单元的主要组件和用于在主要组件发生故障时切换单元的辅助组件。 然后，如果由于主要组件和次要组件造成的单元都能够通过交换机切换单元，则计数由交换机接收，传输或丢弃的单元的步骤，而不包括计数中的任何冗余。
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