-
公开(公告)号：US07046673B2
公开(公告)日：2006-05-16
申请号：US09916096
申请日：2001-07-26
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/108 , H04L49/3081 , H04L2012/5681 , H04Q11/0478
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I≧1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O≧1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
-
2.发明授权Method and apparatus for switching, multicasting multiplexing and demultiplexing an ATM cell 失效用于切换，组播多路复用和解复用ATM信元的方法和装置
公开(公告)号：US5548588A
公开(公告)日：1996-08-20
申请号：US381112
申请日：1995-01-31
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/3081 , H04Q11/0478 , H04L2012/5672
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I.gtoreq.1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O.gtoreq.1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 该交换机包括从ATM网络接收ATM信元的I个输入端口，其中I> / = 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 交换机还包括连接到存储器阵列的O输出端口，其中O> / = 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
-
公开(公告)号：US06278711B1
公开(公告)日：2001-08-21
申请号：US08687888
申请日：1996-07-26
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/108 , H04L49/3081 , H04L2012/5681 , H04Q11/0478
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I≧1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O≧1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 交换机包括从ATM网络接收ATM信元的I输入端口，其中I> = 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 交换机还包括连接到存储器阵列的O输出端口，其中O> = 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
-
4.发明授权Method and apparatus for switching, multicasting, multiplexing and demultiplexing an ATM cell 失效用于ATM信元的切换，组播，复用和解复用的方法和装置
公开(公告)号：US6108335A
公开(公告)日：2000-08-22
申请号：US693996
申请日：1996-08-08
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/3081 , H04Q11/0478 , H04L2012/5672
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I.gtoreq.1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O.gtoreq.1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 该交换机包括从ATM网络接收ATM信元的I个输入端口，其中I> / = 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 交换机还包括连接到存储器阵列的O输出端口，其中O> / = 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
-
公开(公告)号：US5541918A
公开(公告)日：1996-07-30
申请号：US381110
申请日：1995-01-31
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/108 , H04L49/3081 , H04Q11/0478 , H04L2012/5681
摘要： The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I>1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O>1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
摘要翻译： 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列，其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤：在ATM网络的交换机的第一输入端口处接收ATM信元。 然后，可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来，存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来，将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 交换机包括从ATM网络接收ATM信元的I个输入端口，其中I> 1并且是整数。 开关还包括连接到I输入端口的存储器阵列，用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 该交换机还包括连接到存储器阵列的O个输出端口，其中O> 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外，开关包括连接到存储器阵列的控制器，I输入端口和O输出端口，用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作，组播，解复用或多路复用。
-
6.发明授权Method of avoiding or minimizing cost of stateful connections between application servers and S-CSCF nodes in an IMS network with multiple domains 有权避免或最小化具有多个域的IMS网络中应用服务器与S-CSCF节点之间状态连接成本的方法公开(公告)号：US07864936B2
公开(公告)日：2011-01-04
申请号：US11166456
申请日：2005-06-24
IPC分类号： H04M3/42
CPC分类号： H04L65/1006 , H04L65/1016 , H04L67/14 , H04L67/142
摘要： Methods of avoiding or minimizing cost of stateful connections between application servers (ASs) and S-CSCF nodes in an IMS network with multiple domains. S-CSCF service logic is provided and connected to a co-located AS. The IMS includes a network operator administration domain and an MVNO service domain, and the S-CSCF logic and AS are maintained in the same domain, e.g., the MVNO or network operator domain.
摘要翻译： 避免或最小化具有多个域的IMS网络中的应用服务器（AS）和S-CSCF节点之间的状态连接的成本的方法。 提供S-CSCF服务逻辑并将其连接到共同定位的AS。 IMS包括网络运营商管理域和MVNO服务域，并且S-CSCF逻辑和AS被保持在相同的域中，例如MVNO或网络运营商域。
-
7.发明授权公开(公告)号：US07724753B2
公开(公告)日：2010-05-25
申请号：US11370793
申请日：2006-03-08
IPC分类号： H04L12/56
CPC分类号： H04M7/123 , H04L65/1016 , H04L67/14 , H04L67/146 , H04W4/00 , H04W8/26 , H04W48/18 , H04W80/10 , H04W88/18
摘要： A method of controlling and delivering media content from a media server (MS) to a media renderer (MR) utilizing a wide area IMS network for control. The method involves: provisioning a serving node in the IMS network with control point (CP) logic that includes logic to negotiate media content delivery with a least one of an MS and an MR; provisioning a user endpoint (UE) device of the IMS network with control point proxy (CPP) logic that includes logic to negotiate media content delivery and VCR controls to control media presentation; in response to a media content delivery request, invoking the CPP logic and the CP logic to cooperatively negotiate media content delivery between an MS and an MR that uses local wireless or land line connections when possible in order to minimize wide area bandwidth usage.
摘要翻译： 一种使用广域IMS网络来控制媒体内容从媒体服务器（MS）到媒体渲染器（MR）的控制和传送的方法。 该方法包括：利用包括与MS和MR中的至少一个协商媒体内容传送的逻辑的控制点（CP）逻辑来为IMS网络中的服务节点提供服务; 提供具有控制点代理（CPP）逻辑的IMS网络的用户端点（UE）设备，该逻辑包括协商媒体内容传送和VCR控制以控制媒体呈现的逻辑; 响应于媒体内容递送请求，调用CPP逻辑和CP逻辑以在可能的情况下在MS和使用本地无线或陆线连接的MR之间协调协商媒体内容传送，以便最小化广域带宽使用。
-
公开(公告)号：US5333268A
公开(公告)日：1994-07-26
申请号：US946242
申请日：1992-09-16
申请人： David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Bradley C. Kuszmaul , Charles E. Leiserson , David S. Wells , Monica C. Wong , Shaw-Wen Yang , Robert C. Zak
发明人： David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Bradley C. Kuszmaul , Charles E. Leiserson , David S. Wells , Monica C. Wong , Shaw-Wen Yang , Robert C. Zak
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
摘要翻译： 数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。 命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。 数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。
-
9.再颁专利公开(公告)号：USRE44412E1
公开(公告)日：2013-08-06
申请号：US13232432
申请日：2011-09-14
IPC分类号： H04L12/56
CPC分类号： H04M7/123 , H04L65/1016 , H04W4/00 , H04W8/26 , H04W88/18
摘要： A method of controlling and delivering media content from a media server (MS) to a media renderer (MR) utilizing a wide area IMS network for control. The method involves: provisioning a serving node in the IMS network with control point (CP) logic that includes logic to negotiate media content delivery with a least one of an MS and an MR; provisioning a user endpoint (UE) device of the IMS network with control point proxy (CPP) logic that includes logic to negotiate media content delivery and VCR controls to control media presentation; in response to a media content delivery request, invoking the CPP logic and the CP logic to cooperatively negotiate media content delivery between an MS and an MR that uses local wireless or land line connections when possible in order to minimize wide area bandwidth usage.
摘要翻译： 一种使用广域IMS网络来控制媒体内容从媒体服务器（MS）到媒体渲染器（MR）的控制和传送的方法。 该方法包括：利用包括与MS和MR中的至少一个协商媒体内容传送的逻辑的控制点（CP）逻辑来为IMS网络中的服务节点提供服务; 提供具有控制点代理（CPP）逻辑的IMS网络的用户端点（UE）设备，该逻辑包括协商媒体内容传送和VCR控制以控制媒体呈现的逻辑; 响应于媒体内容递送请求，调用CPP逻辑和CP逻辑以在可能的情况下在MS和使用本地无线或陆线连接的MR之间协调协商媒体内容传送，以便最小化广域带宽使用。
-
公开(公告)号：US06259693B1
公开(公告)日：2001-07-10
申请号：US08919830
申请日：1997-08-28
IPC分类号： H04Q1100
CPC分类号： H04L49/405 , H04L49/255 , H04L49/3081 , H04L2012/5627 , H04L2012/5635 , H04Q11/0478
摘要： An apparatus and method for enabling the combination of multiple streams of data cells into a single thread. By enabling plural input ports of an intermediate device to access a single parallel output port of the device, plural network switch elements share a single thread through a switch fabric. For instance, the method and apparatus permit interleaving the relatively low bandwidth cell outputs of two ATM network switch central control processors onto a single thread routed through an interconnected switch fabric. Certain of these cells are received from the switch fabric at a parallel input of the intermediate device, then routed to one of plural serial output ports. Pacing of cells provided to the plural serial input ports prevents exceeding the shared thread bandwidth.
摘要翻译： 一种用于使多个数据单元流组合成单个线程的装置和方法。 通过使中间设备的多个输入端口能够访问设备的单个并行输出端口，多个网络交换机单元通过交换结构共享单个线程。 例如，该方法和装置允许将两个ATM网络交换机中央控制处理器的相对低带宽的小区输出交织到通过互连的交换结构路由的单个线程上。 这些单元中的某些在中间设备的并行输入处从交换结构接收，然后被路由到多个串行输出端口中的一个。 提供给多个串行输入端口的单元的起搏防止超过共享线程带宽。
-
-
-
-
-
-
-
-
-
搜索结果
36 条记录 (耗时 0.03 秒)