公开(公告)号：US20040183809A1

公开(公告)日：2004-09-23

申请号：US10765230

申请日：2004-01-27

发明人： Lawrence Chee ,  Barinder Singh Rai ,  Brett Cheng

IPC分类号： G06F012/06

CPC分类号： G06T3/606 ,  G06T2200/28

摘要： A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address nullas isnull or translates the address to represent a portrait-oriented display address. A refresh address generator operates alternatively in column-forward and column-reverse modes, and additionally operates alternatively in row forward and row reverse modes to selectively rotate the image.

摘要翻译： 用于将面向肖像的软件地址翻译成面向纵向的横向配置的显示地址的系统。 基于显示设备的方向，地址转换系统可以“按原样”传递软件地址，或者转换地址以表示面向纵向的显示地址。 刷新地址发生器以列前进和列反向模式交替运行，并且另外以行前进和行倒退模式另行操作以选择性地旋转图像。

公开(公告)号：US20030174137A1

公开(公告)日：2003-09-18

申请号：US10096066

申请日：2002-03-12

发明人： Philip C. Leung ,  Michael G. Lavelle ,  Elena M. Ing

IPC分类号： G09G005/39 ,  G06F012/06

CPC分类号： G09G5/39 ,  G09G5/14 ,  G09G2360/121 ,  G09G2360/126

摘要： A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

摘要翻译： 图形系统包括帧缓冲器，其包括一个或多个存储器设备和耦合到帧缓冲器的帧缓冲器接口。 帧缓冲器中的每个存储器件包括N个存储体。 每个N个存储体包括多个页面，并且每个页面被配置为存储对应于屏幕区域的一部分的数据。 帧缓冲器接口被配置为生成用于存储对应于帧缓冲器中的数据帧的数据的地址。 该框架包括多个屏幕区域。 帧缓冲器接口被配置为生成与该数据相对应的地址，并且向帧缓冲器提供地址。 生成地址，使得N个存储体中的每一个存储对应于屏幕区域的水平组内的每N个屏幕区域中的一个的一部分的数据。

公开(公告)号：US20040193778A1

公开(公告)日：2004-09-30

申请号：US10819194

申请日：2004-04-07

申请人： Renesas Technology Corp.

发明人： Makoto Ishikawa ,  Fumio Arakawa

IPC分类号： G06F012/06

CPC分类号： G06F9/383 ,  G06F9/342 ,  G06F12/06 ,  G06F12/0846 ,  G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

摘要： In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at a high memory-accessing speed is provided. Because memory types can often be differentiated based only on partial bits of the address obtained by addition, a partial bit adder and decision logic are used to make this differentiation at high speed. Because the partial addition preferably does not take into account the possible carry from the lower bits, two types of memories are chosen from memories and are both operated in case the carry should be null1null and in case it should be null0.null The result is chosen by a multiplexor and is output. A determination of the entry address of the memory may be similarly carried out by dividing the memory into odd and even entry number banks and utilizing a partial bit adder. Then, both banks may be activated with the results of the partial bit adder as entries, and one of the results is chosen for output.

摘要翻译： 在存储器访问过程中，通过识别可以在不降低操作速度的情况下激活的存储器的类型以及通过降低功耗来提供能够以高存储器访问速度操作的数据处理器。 由于存储器类型通常仅基于通过相加获得的地址的部分比特来区分，所以使用部分比特加法器和判定逻辑以高速进行该区分。 由于部分加法优选不考虑来自较低位的可能的进位，所以从存储器中选择两种类型的存储器，并且在进位应当为“1”的情况下并且在“0”的情况下都会运行。 结果由多路复用器选择并输出。 存储器的输入地址的确定可以类似地通过将存储器划分为奇数和偶数入口号组并利用部分位加法器来执行。 然后，可以使用部分位加法器的结果作为条目来激活两个存储体，并且选择其中一个结果用于输出。

公开(公告)号：US20040172516A1

公开(公告)日：2004-09-02

申请号：US10605646

申请日：2003-10-15

发明人： Li-Chun Tu ,  Ping-Sheng Chen ,  Pao-Ching Tseng ,  Hung-Cheng Kuo

IPC分类号： G06F012/06

CPC分类号： G06F12/0623

摘要： A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address extender, and adding bits to stack addresses with a stack pointer generator so that the processor is capable of accessing memory addresses larger than the bit width of the command set of the processor. The method also includes carrying over the bits when the stack address exceeds the limit of the conventional memory and accessing the stack data exceeding the limit of the conventional memory in the extended memory.

摘要翻译： 一种用于增加处理器内部存储器的方法。 该方法包括在处理器中提供扩展存储器，向位地址扩展器添加比特到数据地址和寄存器地址，以及使用堆栈指针生成器将位添加到堆栈地址，使得处理器能够访问大于位宽的存储器地址 的处理器的命令集。 该方法还包括当堆栈地址超过常规存储器的限制并且访问超过扩展存储器中的常规存储器的限制的堆栈数据时承载位。

公开(公告)号：US20040130553A1

公开(公告)日：2004-07-08

申请号：US10739344

申请日：2003-12-19

申请人： Canon Kabushiki Kaisha

发明人： Katsutoshi Ushida ,  Yuichi Naoi ,  Yoshiaki Katahira ,  Yasuyuki Nakamura ,  Koichi Morishita ,  Makoto Fukuo

IPC分类号： G09G005/39 ,  G06F012/06

CPC分类号： G06T1/60 ,  G06T1/0007

摘要： To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

摘要翻译： 为了提供与CCD和CIS兼容的图像处理技术，其控制存储器中的每个设备读取的图像数据的存储器以及用于每个矩形区域的存储的数据的读取以获得高的存储器效率，图像处理装置 存储区域控制部分，对于在第一存储器上位映射的图像数据，设置在主扫描方向和副扫描方向上分割的矩形区域，生成地址信息以读出对应于矩形的图像数据的地址信息 区域，与设置的矩形区域对应的存储器控​​制部分，读出对应于矩形区域的图像数据的存储器控​​制部分，并且根据生成的地址信息将图像数据DMA传送到第二存储器;以及图像处理部件，其执行 通过使用第二存储器对DMA传送数据的每个矩形区域进行图像处理。

公开(公告)号：US20030063092A1

公开(公告)日：2003-04-03

申请号：US09964802

申请日：2001-09-28

发明人： Gavril Margittai ,  Zeev Sperber ,  Gabi Malka

IPC分类号： G06F015/80 ,  G06F013/18 ,  G06T011/40 ,  G06F012/06

CPC分类号： G06T15/04

摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

摘要翻译： 用于平衡多管道纹理引擎中的并行纹理管道发出的存储器请求的仲裁机制。 该机制确保，由于纹理引擎处理多边形纹理，所有与给定图形纹理的一部分相关联的存储器请求将在任何纹理流水线发布对图形的另一部分的存储器请求之前由所有纹理管线发出 质地。 因此，本发明平衡了在一起操作的并行纹理管线之间的图形纹理处理，从而提高处理效率并防止死锁状况。

公开(公告)号：US20010026279A1

公开(公告)日：2001-10-04

申请号：US09813035

申请日：2001-03-21

申请人： Fuji Photo Film Co., Ltd.

发明人： Masanari Asano

IPC分类号： G09G005/39 ,  G06F012/06

CPC分类号： H04N7/035 ,  G09G5/39 ,  G09G2360/12 ,  H04N5/44504 ,  H04N21/4435 ,  H04N21/488 ,  H04N21/4884 ,  H04N21/4888

摘要： A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.

摘要翻译： 存储器控制单元使用存储器控制器来调整和设置存储器的存储空间中的图像数据区域的地址和与存储区域相邻的窗口区域的地址。 存储器控制单元存储在指定的地址位置处提供的图像数据以外的数据，并且当控制信号被发送到存储器时，从存储器读出包括存储在窗口区域中的数据的图像数据。 在消隐期间将从窗口区读出的数据插入预定位置。

公开(公告)号：US20010003200A1

公开(公告)日：2001-06-07

申请号：US09732053

申请日：2000-12-06

发明人： Toru Utsumi

IPC分类号： G06F012/06

CPC分类号： G11C8/00 ,  G11C8/04

摘要： If a word line is selected by inputting an immediate value and base address, whose values are determined at different timings, to an adder, the access speed decreases due to the constraint of the base address whose value is determined at a later timing. According to this invention, decoding is performed by inputting only the immediate value whose value is determined earlier to an address decoder AD. Thereafter, a word line WL is selected by performing rotation using the base address whose value is determined at a later timing. This makes it possible to start decoding processing without waiting for the determination of the value of the base address and increase the overall access speed.

摘要翻译： 如果通过将加法器的值以不同的定时输入立即值和基地址来选择字线，则由于在稍后的时间确定其值的基地址的约束，访问速度降低。 根据本发明，通过仅将前面确定的值的立即值仅输入到地址译码器AD来进行解码。 此后，通过使用其值在稍后的时间确定的基地址执行旋转来选择字线WL。 这使得可以在不等待基地址的值的确定并且增加总的访问速度的情况下开始解码处理。

公开(公告)号：US20040255094A1

公开(公告)日：2004-12-16

申请号：US10765092

申请日：2004-01-28

申请人： ARM LIMITED

发明人： David James Seal

IPC分类号： G06F012/06

CPC分类号： G06F9/342 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/322 ,  G06F9/324

摘要： A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.

摘要翻译： 提供数据处理系统2，其支持地址偏移生成指令，其使用传统指令编码中的先前冗余位来编码地址偏移值的位，同时保持与该遗留编码的向后兼容性。

公开(公告)号：US20030217245A1

公开(公告)日：2003-11-20

申请号：US10147795

申请日：2002-05-17

申请人： International Business Machines Corporation

发明人： Jeffrey S. Chase ,  Ronald P. Doyle ,  David L. Kaminsky

IPC分类号： G06F012/06

CPC分类号： G06F3/0601 ,  G06F9/5011 ,  G06F9/505 ,  G06F2003/0697 ,  H04L67/1097

摘要： A method for enforcing a service discrimination policy in a storage system. The service discrimination policy enforcement method can include monitoring load metrics for physical resources required to access content stored within the storage system. A request to access the content stored within the storage system can be received. A corresponding guaranteed service level can be identified from the request. In consequence, a particular one of the physical resources can be selected to service the request based upon a determination that the selected physical resource can service the request while satisfying the guaranteed service level at a load indicated by the monitored load metrics.

摘要翻译： 一种用于在存储系统中执行服务辨别策略的方法。 服务辨别策略执行方法可以包括监视访问存储在存储系统内的内容所需的物理资源的负载度量。 可以接收访问存储在存储系统中的内容的请求。 可以从请求中识别相应的保证服务级别。 因此，可以选择物理资源中的特定一个来基于所选择的物理资源可以在由所监视的负载度量指示的负载满足保证服务水平的情况下服务于该请求的确定来服务该请求。