摘要:
The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
摘要:
The disclosure discloses a data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV, wherein the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. By means of the disclosure, the problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.
摘要:
The present disclosure presents methods and apparatuses for operating a multi-display device to mitigate the effects of image interruption due to bezels between individual display devices. For example, a method of operating a video device includes generating a bezel-corrected image which spans a plurality of display devices, the bezel-corrected image including masked image pixels, wherein the masked image pixels are associated with a bezel of at least one of the plurality of display devices. Such example methods may further include detecting a head position change of a user and displaying one or more of the masked image pixels on at least one of the plurality of display devices based on the head position change.
摘要:
Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.
摘要:
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要:
A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.
摘要:
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.
摘要:
A liquid crystal display includes a display unit displaying an image in response to a driving signal, a driving unit outputting the driving signal to the display unit in response to a plurality of control signal, and a controller outputting the plurality of control signals and image data. The controller includes a plurality of timing controllers providing the image data and the plurality of control signals and a storage device. The plurality of timing controllers share the storage device and may be either connected in series or parallel.
摘要:
A visual messaging system and device can employ high efficiency LEDs and current driven versus voltage driven circuits to reduce power consumption and enable the device to be powered from IEEE 802.3af (Power over Ethernet (PoE)) standard based power sources. The device can be powered from a local area network (LAN) connection using PoE, and does not require a separate AC power supply. The present invention also uses a 1× yellow algorithm to create the yellow color with one half the instantaneous current of previous circuits. The device can incorporate multiple message inputs for receiving and displaying messages having different priorities, allowing higher priority messages to override lower priority messages.
摘要:
A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.