公开(公告)号：US06550013B1

公开(公告)日：2003-04-15

申请号：US09388952

申请日：1999-09-02

申请人： Gilles Gervais ,  James D. Wagoner ,  Stephen D. Weitzel

发明人： Gilles Gervais ,  James D. Wagoner ,  Stephen D. Weitzel

IPC分类号： G06F108

CPC分类号： G06F1/08

摘要： A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.

摘要翻译： 实现了存储器时钟发生器装置和方法。 从处理器时钟产生存储器时钟“开环”。 处理器时钟被选通并通过移位寄存器传播。 从移位寄存器中抽出的一组输出与多个控制信号一起被解码，并且以“或”逻辑进行解码，以生成可以以存储器时钟速率的预定倍数运行的时钟输出。 时钟输出可以具有存储器时钟周期与处理器时钟周期的多个比率中的一个。 控制信号选择比例。 时钟发生器可以异步启动，并且另外，发生器向具有与时钟发生器的开始具有预定时间关系的边沿的处理器输出信号。

公开(公告)号：US06493830B2

公开(公告)日：2002-12-10

申请号：US09343185

申请日：1999-06-30

申请人： Masafumi Kamei

发明人： Masafumi Kamei

IPC分类号： G06F108

CPC分类号： H04N5/3577 ,  H04N5/372

摘要： Video data (default data in case of a black original) output from a CCD line sensor 405 upon reading an image while a light source is kept OFF corresponds to beat noise contained in video data obtained upon reading an image while the light source is ON. After the beat noise data is stored, the correction data stored in a correction data storage unit is subtracted from video data read by a normal technique while the light source is ON in a correction memory, thus executing correction for removing beat noise. After the beat noise is removed in this way, when an image is formed under the control of a printer control unit, an image free from any beat noise can be obtained as an output image.

摘要翻译： 在光源保持关闭时读取图像时从CCD线传感器405输出的视频数据（黑色情况下的默认数据）对应于在光源接通时在读取图像时获得的视频数据中包含的拍频。 在存储节拍噪声数据之后，在校正存储器中光源接通时，通过普通技术读取的视频数据中减去存储在校正数据存储单元中的校正数据，从而执行用于去除拍频噪声的校正。 在以这种方式去除了节拍噪声之后，当在打印机控制单元的控制下形成图像时，可以获得没有任何拍噪噪声的图像作为输出图像。

公开(公告)号：US06425089B1

公开(公告)日：2002-07-23

申请号：US09299718

申请日：1999-04-26

申请人： Hsi-Jung Tsai

发明人： Hsi-Jung Tsai

IPC分类号： G06F108

CPC分类号： G06F13/423 ,  G06F1/04

摘要： A method is provided for use on a PCI-compliant (Peripheral Component Inter-connection) interface card having a UART (Universal Asynchronous Receiver-Transmitter) unit to generate a near-1.8432 MHz clock signal for clocking the UART unit. This method includes a first step of dividing a selected PCI clock signals, such as the 33 MHz PCI clock signal, from the PCI local bus by a predetermined integer frequency divisor; and a second step of multiplying the resulted frequency from the division by a predetermined integer frequency multiplier that allows the resulted frequency to be substantially close to 1.8432 MHz to serve as the intended clock signal to the UART unit. Preferably, the integer frequency multiplier is in the range equal to or greater than 8. This method can generate a more precise clock signal for the UART unit on the PCI-compliant interface card without having to use an external crystal oscillator. Moreover, the method requires only a frequency divider without a frequency multiplier to implement. The method allows the resulted frequency deviation to be smaller than the prior art and also allows a reduction in the implementation cost as compared to the prior art.

摘要翻译： 提供了一种用于具有UART（通用异步收发器）单元的PCI兼容（外围组件互连）接口卡的方法，用于产生用于为UART单元计时的近1.8432MHz时钟信号。 该方法包括将来自PCI本地总线的所选PCI时钟信号（例如33MHz PCI时钟信号）除以预定的整数倍频器的第一步骤; 以及将得到的频率从除法乘以预定的整数倍频器的第二步骤，其允许所得到的频率基本上接近1.8432MHz，以用作到UART单元的预期时钟信号。 优选地，整数倍频器在等于或大于8的范围内。该方法可以在PCI兼容接口卡上为UART单元产生更精确的时钟信号，而不必使用外部晶体振荡器。 此外，该方法仅需要没有倍频器的分频器来实现。 该方法允许所得到的频率偏差小于现有技术，并且与现有技术相比还允许降低实施成本。

公开(公告)号：US06175929B1

公开(公告)日：2001-01-16

申请号：US09146574

申请日：1998-09-03

申请人： Hsien-Yueh Hsu ,  Tien-Wei Lin

发明人： Hsien-Yueh Hsu ,  Tien-Wei Lin

IPC分类号： G06F108

CPC分类号： G06F1/08 ,  H03L7/00

摘要： A system clock switch circuit for a computer main board sends a reset signal to the chipset from the clock generator or a additional reset signal generator as soon as the system clock frequency is changed by the CPU. In result, the computer main board restarts with a new system clock frequency after the reset signal is canceled to avoid the malfunctions caused by the non-synchronization between the system clock frequency and the clock frequencies of peripherals.

摘要翻译： 一旦系统时钟频率由CPU改变，用于计算机主板的系统时钟切换电路就从时钟发生器或附加复位信号发生器向芯片组发送复位信号。 结果，在复位信号被取消之后，计算机主板以新的系统时钟频率重新启动，以避免系统时钟频率与外设的时钟频率之间的不同步造成的故障。

公开(公告)号：US06687841B1

公开(公告)日：2004-02-03

申请号：US09673820

申请日：2000-12-12

申请人： Shoji Marukawa

发明人： Shoji Marukawa

IPC分类号： G06F108

CPC分类号： G11B20/10037 ,  G11B20/1258 ,  G11B20/1403 ,  H03L7/091 ,  H03L7/093 ,  H03L7/10

摘要： A clock generation circuit of the present invention extracts a phase error signal of a digital signal obtained from a recording medium (1) by a phase comparator (4), filters the phase error signal by a loop filter (5). In a first embodiment it converts the signal into an analog signal by a minute control D/A converter (6), detects whether the signal is within a set range by a range detector (9), generates a modulation reference signal by a modulation reference signal generator (10), modulates the modulation reference signal by a pulse width modulator (11), adds a frequency set value and the modulation reference signal by an adder (12), converts the addition result into an analog signal by a rough control D/A converter (13), cuts high-band components of the analog signal by a low-pass filter (14), adds the analog signals output from the minute control D/A converter (6) and the low-pass filter (14) by an analog adder (7), and outputs a clock signal by a voltage controlled oscillator (8) on the basis of an output signal of the analog adder (7). Thereby, a clock signal which can continuously lock a wide frequency range can be generated. In a second embodiment the loop filter output is oversampled (15), then interpolated (16) and modulated by a multivalued delta sigma modulator.

摘要翻译： 本发明的时钟发生电路通过相位比较器（4）提取从记录介质（1）获得的数字信号的相位误差信号，通过环路滤波器（5）对相位误差信号进行滤波。 在第一实施例中，微分控制D / A转换器（6）将信号转换为模拟信号，通过范围检测器（9）检测信号是否在设定范围内，通过调制参考产生调制参考信号 信号发生器（10），通过脉宽调制器（11）调制调制参考信号，通过加法器（12）将频率设定值和调制参考信号相加，通过粗略控制D将相加结果转换为模拟信号 / A转换器（13），通过低通滤波器（14）切断模拟信号的高频分量，将从微控制D / A转换器（6）和低通滤波器（14）输出的模拟信号相加 ），并且通过压控振荡器（8）基于模拟加法器（7）的输出信号输出时钟信号。 因此，可以产生可以连续锁定宽频率范围的时钟信号。 在第二实施例中，环路滤波器输出被过采样（15），然后被内插（16）并由多值Δ-Σ调制器调制。

公开(公告)号：US06466073B1

公开(公告)日：2002-10-15

申请号：US09670584

申请日：2000-09-27

申请人： Yoshio Yukinari ,  Kouichi Ishimi

发明人： Yoshio Yukinari ,  Kouichi Ishimi

IPC分类号： G06F108

CPC分类号： G06F1/08 ,  H03L7/16

摘要： Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequency-divided clocks such that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency, is slightly delayed against all of the other generated frequency-divided clocks. When changing the frequency of an output clock, a multiplexer switches from a previously selected one of the plurality of generated frequency-divided clocks to a desired clock in responsive to a control signal. The desired frequency-divided clock is then furnished as the output clock. Even when the plurality of frequency-divided clocks are not in phase with each other because of unit-to-unit variation when manufacturing the frequency dividing circuit, or due to changes in the operating conditions such as ambient temperature and voltages, the first clock pulse generated when the multiplexer performs the switching operation cannot have a shorter pulse width than pulses of the frequency-divided clock having the highest frequency.

摘要翻译： 时钟发生电路包括一个分频电路，用于将输入时钟的频率除以彼此不同的多个预定分频比，以产生多个分频时钟，使得分频时钟由 最小分频比，即具有最高频率的分频时钟，对所有其它产生的分频时钟稍微延迟。 当改变输出时钟的频率时，响应于控制信号，多路复用器从多个生成的分频时钟中的先前选择的一个切换到期望的时钟。 然后将期望的分频时钟作为输出时钟。 即使当制造分频电路时由于单位变化而导致多个分频时钟彼此不相位，或者由于诸如环境温度和电压的操作条件的变化，第一时钟脉冲 当多路复用器执行切换操作时产生的脉冲宽度不能比具有最高频率的分频时钟的脉冲具有更短的脉冲宽度。

公开(公告)号：US06421786B1

公开(公告)日：2002-07-16

申请号：US09266781

申请日：1999-03-12

申请人： Shinji Yoshihara

发明人： Shinji Yoshihara

IPC分类号： G06F108

CPC分类号： G06F1/14

摘要： To allow an AP which performs operation based on a time of a system clock and another AP which performs operation based on a user-specified time to be executed concurrently in a data processing unit with only one system clock without having to change the time of the system clock, virtual system time setting means 5 receive a command or job start date and/or time from an input/output unit 2 and store it in a virtual system time storage area 4. In response to a system date acquisition function 6 or a system time acquisition function 7 from a command or a job, virtual system time converting means return either the date of the system clock when the date is not stored in the virtual system time storage area 4 or the date stored in the date storage area when the date is stored therein. The means also return either the time of the system clock when the time is not stored in the virtual system time storage area or the time of said system clock plus the time stored in said time storage area when the time is stored therein.

摘要翻译： 为了允许基于系统时钟的时间执行操作的AP和基于用户指定时间执行操作的另一个AP在仅具有一个系统时钟的数据处理单元中同时执行，而不必改变 系统时钟，虚拟系统时间设置装置5从输入/输出单元2接收命令或作业开始日期和/或时间，并将其存储在虚拟系统时间存储区域4.响应于系统日期获取功能6或 系统时间获取功能7，虚拟系统时间转换装置在日期不存储在虚拟系统时间存储区域4中时返回系统时钟的日期，或者当存储在日期存储区域中的日期时，返回系统时钟的日期 日期存储在其中。 当时间不存储在虚拟系统时间存储区域中时，系统时钟的时间还是系统时钟的时间加上存储在所述时间存储区域中的时间加上存储在所述时间存储区域中的时间。

公开(公告)号：US06195753B1

公开(公告)日：2001-02-27

申请号：US09093104

申请日：1998-06-08

申请人： Yousuke Nakamura

发明人： Yousuke Nakamura

IPC分类号： G06F108

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/3869 ,  Y02D10/128 ,  Y02D10/171

摘要： An information processing apparatus includes an instruction memory, an instruction register, a plurality of function blocks, an instruction/state decoder, and a clock supply/stop circuit. The instruction memory stores instructions. An instruction is loaded from the instruction memory into the instruction register. The function blocks perform a basic operation required for execution of the instruction. The instruction/state decoder decodes the instruction read out from the instruction register, and also decodes a control signal used for notification of a state between the function blocks. The clock supply/stop circuit supplies a clock signal to a function block, of the plurality of function blocks, which is required for execution of the decoded instruction and needs to operate, on the basis of an output signal from the instruction/state decoder.

摘要翻译： 信息处理装置包括指令存储器，指令寄存器，多个功能块，指令/状态解码器和时钟供应/停止电路。 指令存储器存储指令。 指令从指令存储器加载到指令寄存器中。 功能块执行执行指令所需的基本操作。 指令/状态解码器对从指令寄存器读出的指令进行解码，并对用于通知功能块之间的状态的控制信号进行解码。 时钟供应/停止电路根据来自指令/状态解码器的输出信号向执行解码指令所需的多个功能块的功能块提供时钟信号，并需要操作。

公开(公告)号：US06182235B2

公开(公告)日：2001-01-30

申请号：US09224813

申请日：1998-12-30

申请人： Edward Tang Kwai Ma ,  Frank Victor Taylor, III ,  Sai Bun Samuel Wong

发明人： Edward Tang Kwai Ma ,  Frank Victor Taylor, III ,  Sai Bun Samuel Wong

IPC分类号： G06F108

CPC分类号： G06F1/025

摘要： A microcontroller integrated circuit incorporating a user configurable pulse width modulator. The pulse width modulator circuitry is configurable to be a single, for example 32-bit pulse width modulator, or a plurality of pulse width modulators each having a bit width that is divisible by the single 32-bit pulse width modulator (e.g., 2, 4, 8 or 16-bit pulse width modulators).

摘要翻译： 包含用户可配置脉宽调制器的微控制器集成电路。 脉冲宽度调制器电路可配置为单个例如32位脉冲宽度调制器或多个脉冲宽度调制器，每个脉冲宽度调制器具有可由单个32位脉冲宽度调制器（例如，2， 4或8位或16位脉宽调制器）。

公开(公告)号：US06725391B2

公开(公告)日：2004-04-20

申请号：US09740921

申请日：2000-12-19

申请人： Gary L. Swoboda

发明人： Gary L. Swoboda

IPC分类号： G06F108

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The oscillator clock circuit operates in several modes selected by an externally writeable control register. The clock circuit synchronizes with the function clock signal or a reference clock signal as selected by the control register. Pre-scalers are employed in two paths to scale the oscillator clock frequency. The clock circuit also includes calibration and test modes selected by the control register.

摘要翻译： 构成便于调试和仿真的集成电路包括功能时钟电路和与功能时钟同步工作的操作电路。 跟踪触发电路在检测到运算电路内的预定条件时触发跟踪操作。 FIFO缓冲区接收通过跟踪端口导出的跟踪数据。 集成电路包括可以与功能时钟或参考时钟同步的振荡器时钟电路。 振荡器时钟电路以外部可写控制寄存器选择的多种模式工作。 时钟电路与功能时钟信号或由控制寄存器选择的参考时钟信号同步。 预分频器采用两个路径来缩放振荡器时钟频率。 时钟电路还包括由控制寄存器选择的校准和测试模式。