METHOD AND DEVICE FOR PERFORMING PAC CODE-BASED HYBRID DECODING IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20240171308A1

    公开(公告)日:2024-05-23

    申请号:US18069072

    申请日:2022-12-20

    IPC分类号: H04L1/00 H03M13/23 H03M13/29

    摘要: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than 4G communication systems such as LTE systems. The disclosure relates to a method and device for dynamically selecting, or simultaneously performing, PAC code-based fano decoding and/or list decoding in a wireless communication system. The method for performing PAC code-based decoding by a reception device in a wireless communication system comprises identifying a specific criterion variable related to a channel state for selecting at least one of fano decoding or list decoding for a signal received from a transmission device, comparing the specific criterion variable related to the channel state with a threshold, performing the fano decoding in case that the specific criterion variable related to the channel state satisfies the threshold, and performing the list decoding in case that the specific criterion variable related to the channel state does not satisfy the threshold.

    RECEIVER RECEIVING A SIGNAL INCLUDING PHYSICAL LAYER FRAMES, AND INCLUDING A CONVOLUTIONAL DEINTERLEAVER AND A DEINTERLEAVER SELECTOR

    公开(公告)号:US20220200629A1

    公开(公告)日:2022-06-23

    申请号:US17693995

    申请日:2022-03-14

    IPC分类号: H03M13/27 H03M13/23 H04L1/00

    摘要: A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

    Receiver receiving a signal including physical layer frames, and including a convolutional deinterleaver and a deinterleaver selector

    公开(公告)号:US11303304B2

    公开(公告)日:2022-04-12

    申请号:US16198921

    申请日:2018-11-23

    申请人: SONY CORPORATION

    摘要: A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

    Distributed data storage system data decoding and decryption

    公开(公告)号:US11233643B1

    公开(公告)日:2022-01-25

    申请号:US16574793

    申请日:2019-09-18

    摘要: A method for execution by a processing module of a distributed storage includes transmitting a request to retrieve a set of encoded data slices (EDSs) to a plurality of storage nodes followed by receiving a threshold number of EDSs from one or more of the plurality of storage nodes, and decoding the EDSs to produce a transposed encrypted data segment. The method continues with the processing module partitioning the encrypted data segment into an encoded encryption key and encrypted data, performing a hash function on the encrypted data to produce a digest resultant and combining the digest resultant with the encoded encryption key to generate combined key data. The method then continues with decoding the combined key data to recover an encryption key and decrypting the encrypted data using the encryption key to recover a data segment.

    Fast copy through controller
    6.
    发明授权

    公开(公告)号:US11177012B1

    公开(公告)日:2021-11-16

    申请号:US16910905

    申请日:2020-06-24

    摘要: A method and apparatus for a CTC data copy operation, in that modification, and subsequent encoding only affects a small portion of metadata associated with copied data. By modifying and re-encoding only this small portion of metadata, a small portion of the parity data for the copied data requires updating. In embodiments where there are no errors in the read data to be copied (e.g., from an SLC portion of a NAND), decoding, modification, and encoding, may be done in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits may be predetermined and combined (e.g., by XOR) to update the metadata parity bits.

    Transmission apparatus and method, and reception apparatus and method

    公开(公告)号:US11139837B2

    公开(公告)日:2021-10-05

    申请号:US16872863

    申请日:2020-05-12

    发明人: Yutaka Murakami

    摘要: A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

    Cryptographic computer machines with novel switching devices

    公开(公告)号:US11093213B1

    公开(公告)日:2021-08-17

    申请号:US16172584

    申请日:2018-10-26

    申请人: Peter Lablans

    发明人: Peter Lablans

    摘要: Operational n-state digital gates execute Finite Lab-transformed (FLT) n-state switching functions or n-state switching function tables to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output, with n>2, n>3 and n>64. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and multiplication over finite field GF(n) or by addition and multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer characterized by known operations. Known cryptographic methods executed with novel n-state digital gates include encryption/decryption, public key generation, message digest and Elliptic Curve Cryptography wherein one n-state switching function is replaced by an FLT'ed n-state switching function.

    SYSTEMS AND METHODS FOR DETECTING OR PREVENTING FALSE DETECTION OF THREE ERROR BITS BY SEC

    公开(公告)号:US20210194506A1

    公开(公告)日:2021-06-24

    申请号:US16816093

    申请日:2020-03-11

    发明人: David M. Symons

    摘要: Various implementations described herein relate to correcting errors in Dynamic Random Access Memory (DRAM). A memory controller uses an Error Correcting Code (ECC) to store an encoded data word within a DRAM die. The DRAM die is communicatively coupled the memory controller by a memory data bus. The DRAM die includes on-die error correction for data bits stored in the DRAM. Upon reading the encoded data word, the memory controller corrects and detects one or more errors. The one or more errors are introduced by at least one of the on-die error correction of the DRAM die or the memory data bus.