公开(公告)号：US20110102066A1

公开(公告)日：2011-05-05

申请号：US12650507

申请日：2009-12-30

Applicant: Sin Hyun JIN ,  Jong Chern LEE

Inventor： Sin Hyun JIN ,  Jong Chern LEE

IPC: H03H11/40

CPC classification number: G11C5/04 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/00014

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

Abstract translation: 具有多个堆叠芯片的半导体装置包括：贯穿硅通孔（TSV），被配置为将多个芯片耦合在一起并且被配置为串联耦合到多个压降单元; 多个信号转换单元，每个信号转换单元被配置为将从多个芯片中的相应一个芯片的电压降单元输出的电压转换为数字代码信号，并将数字代码信号提供为对应的一个芯片识别信号 的多个芯片; 以及多个芯片选择信号生成单元，每个芯片选择信号生成单元被配置为将芯片识别信号与芯片选择识别信号进行比较，以生成多个芯片中相应的一个芯片的芯片选择信号。

公开(公告)号：US20110102006A1

公开(公告)日：2011-05-05

申请号：US12651066

申请日：2009-12-31

Applicant: Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

Inventor： Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

IPC: G01R31/26 ,  G01R31/3187

CPC classification number: G01R31/318513

Abstract: A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

Abstract translation: 一种用于测试半导体装置的电路包括：测试电压施加单元，被配置为响应于测试模式信号将测试电压施加到穿硅通孔（TSV）的第一端;以及检测单元，被配置为连接到第二 结束TSV，并检测从TSV的第二端输出的电流。

公开(公告)号：US20100290306A1

公开(公告)日：2010-11-18

申请号：US12493835

申请日：2009-06-29

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C8/00

CPC classification number: G11C8/04 ,  G11C8/18

Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.

Abstract translation: 用于移位地址的电路包括：移位单元块，被配置为响应于移位控制信号顺序地移位地址信号;以及控制单元块，被配置为使用顺序移位的读取命令生成用于以列单元激活移位单元块的移位控制信号 或写命令。

公开(公告)号：US20100244920A1

公开(公告)日：2010-09-30

申请号：US12491567

申请日：2009-06-25

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.

Abstract translation: 延迟电路包括第一和第二选择性延迟级，每个延迟阶段包括多个单位延迟单元以延迟施加到其上的信号; 以及延迟控制单元，被配置为响应于第一和第二选择信号的代码组合，选择性地将输入信号施加到第一选择延迟级或第二选择性延迟级，并产生输出信号。

公开(公告)号：US07733162B2

公开(公告)日：2010-06-08

申请号：US12327729

申请日：2008-12-03

Applicant: Jong-Sam Kim ,  Jong-Chern Lee

Inventor： Jong-Sam Kim ,  Jong-Chern Lee

IPC: G05F3/02

CPC classification number: G11C11/4085 ,  G11C5/145 ,  G11C11/4074 ,  H02M3/073 ,  H02M2003/077

Abstract: A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump.

Abstract translation: 一种半导体存储装置的泵浦电压产生电路，所述泵送电压产生电路包括：检测单元，被配置为将泵浦电压的电平与参考电压的电平进行比较以产生检测信号;振荡信号发生器，被配置为顺序地产生 响应于所述检测信号的第一振荡信号和第二振荡信号，并且当产生所述第二振荡信号时提升所述第一和第二振荡信号的频率;第一泵，被配置为响应于所述第一振荡 信号，以及第二泵，被配置为响应于所述第二振荡信号执行泵送操作，其中所述第一泵和所述第二泵的输出端子共同连接，并且所述泵浦电压在所述第一泵的输出端子处输出， 第二个泵。

公开(公告)号：US20090167417A1

公开(公告)日：2009-07-02

申请号：US12136429

申请日：2008-06-10

Applicant: Jong Sam KIM ,  Jong Chern LEE

Inventor： Jong Sam KIM ,  Jong Chern LEE

IPC: G05F1/10

CPC classification number: H02M3/073 ,  G11C5/145 ,  H02M1/32 ,  H02M2001/008

Abstract: A charge pumping circuit consumes less current by reducing the number of charge pumps operating simultaneously. The charge pumping circuit includes a voltage sensor that detects a level of a high voltage and outputs a control signal based on the detection result. An oscillator provides an oscillating clock signal in response to the control signal of the voltage sensor, and the oscillator sequentially outputs the clock signal as a plurality of clock signals having shifted phases A plurality of high-voltage pumps are disposed in a plurality of regions to pump the high voltage in response to the clock signals and a different phase is designated for each region.

Abstract translation: 电荷泵浦电路通过减少同时工作的电荷泵的数量来消耗较少的电流。 电荷泵送电路包括检测高电平的电压传感器，并且基于检测结果输出控制信号。 振荡器响应于电压传感器的控制信号提供振荡时钟信号，并且振荡器顺序地输出时钟信号作为多个具有偏移相位的时钟信号，多个高压泵被设置在多个区域中 根据时钟信号泵送高电压，并为每个区域指定不同的相位。

公开(公告)号：US07492646B2

公开(公告)日：2009-02-17

申请号：US11717662

申请日：2007-03-14

Applicant: Jong-Chern Lee ,  Sun-Hye Shin

Inventor： Jong-Chern Lee ,  Sun-Hye Shin

IPC: G11C5/14

CPC classification number: G05F1/465

Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.

Abstract translation: 半导体存储器件的内部电压发生器能够改变待机模式和有源模式之间的驱动能力，以便在待机模式下更快地响应并防止在待机模式下的漏电流。 半导体存储器件的内部电压发生器包括用于产生具有关于待机和有功模式的信息的驱动控制信号的驱动控制器，通过用于将内部电压与待机和有效模式下的参考电压进行比较的驱动控制信号使能的第一电压发生器 模式，用于根据由第一电压发生器进行的比较产生内部电压的第一驱动器，通过用于将内部电压与活动模式中的参考电压进行比较的驱动控制信号使能的第二电压发生器和用于 根据由第二电压发生器执行的比较产生内部电压。

公开(公告)号：US07339397B2

公开(公告)日：2008-03-04

申请号：US11176345

申请日：2005-07-08

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: H03K19/003

CPC classification number: G11C7/1069 ,  G11C7/1051

Abstract: A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and amplified data onto the GIO line, a GIO termination unit driven responsive to a termination signal for rising or falling a voltage level on the GIO line by a preset level, prior to driving the data onto the GIO line by the read driver, and a receiver driven responsive to the read data transmitted through the GIO line for inverting and amplifying the read data to provide inverted and amplified data. This data output apparatus can enable a high rate data transmission by decreasing a swing width of data transmitted via the GIO line and also reduce a coupling noise on adjacent lines.

Abstract translation: 全局输入和输出（GIO）线中的数据输出装置和方法经由GIO线传送数据。 该数据输出装置包括读取驱动器，该读取驱动器响应于用于反相和放大数据的读取数据的输入，以将反相和放大的数据输出到GIO线上;响应终止信号驱动的GIO终端单元，用于上升或下降电压电平 在读取驱动器将数据驱动到GIO线之前，将GIO线上的GIO线和响应于通过GIO线传输的读取数据驱动的接收器进行反相和放大，以提供反相和放大数据 。 该数据输出装置可以通过减小通过GIO线传输的数据的摆幅来实现高速率数据传输，并且还减少相邻线路上的耦合噪声。

公开(公告)号：US07317338B2

公开(公告)日：2008-01-08

申请号：US11182230

申请日：2005-07-15

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: H03K19/0175 ,  H03K19/094

CPC classification number: H03K19/018585 ,  H03K19/0016

Abstract: The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing device controlled by a buffer enable signal, for sensing a logic level of an input data by comparing voltage levels of a reference voltage and the input data, a reference voltage detector for detecting the level of the reference voltage, and a second biasing device controlled by an output signal from the reference voltage detector and parallel connected to the first biasing device.

Abstract translation: 本发明提供一种用于半导体器件的输入缓冲器，通过检测参考电压的电平来减少电流消耗并保持可靠的运行速度。 输入缓冲器包括比较器，具有由缓冲器使能信号控制的第一偏置装置，用于通过比较参考电压和输入数据的电压电平来感测输入数据的逻辑电平;参考电压检测器，用于检测 参考电压和由来自参考电压检测器的输出信号控制并且并联连接到第一偏置装置的第二偏置装置。

公开(公告)号：US20060208762A1

公开(公告)日：2006-09-21

申请号：US11182230

申请日：2005-07-15

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: H03K19/094

CPC classification number: H03K19/018585 ,  H03K19/0016

Abstract: The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing device controlled by a buffer enable signal, for sensing a logic level of an input data by comparing voltage levels of a reference voltage and the input data, a reference voltage detector for detecting the level of the reference voltage, and a second biasing device controlled by an output signal from the reference voltage detector and parallel connected to the first biasing device.

Abstract translation: 本发明提供一种用于半导体器件的输入缓冲器，通过检测参考电压的电平来减少电流消耗并保持可靠的运行速度。 输入缓冲器包括比较器，具有由缓冲器使能信号控制的第一偏置装置，用于通过比较参考电压和输入数据的电压电平来感测输入数据的逻辑电平;参考电压检测器，用于检测 参考电压和由来自参考电压检测器的输出信号控制并且并联连接到第一偏置装置的第二偏置装置。