公开(公告)号：US08760181B2

公开(公告)日：2014-06-24

申请号：US12914424

申请日：2010-10-28

Applicant: Sang-Jin Byeon ,  Jong-Chern Lee

Inventor： Sang-Jin Byeon ,  Jong-Chern Lee

IPC: G01R31/36 ,  G11C5/02

CPC classification number: G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract translation: 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US08482331B2

公开(公告)日：2013-07-09

申请号：US12832549

申请日：2010-07-08

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03K5/135 ,  H03K2005/00104

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract translation: 开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值 延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟 响应代码值。

公开(公告)号：US08451037B2

公开(公告)日：2013-05-28

申请号：US13048185

申请日：2011-03-15

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

Abstract translation: 占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比 信号并输出​​检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

公开(公告)号：US08314476B2

公开(公告)日：2012-11-20

申请号：US12833672

申请日：2010-07-09

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US20120154002A1

公开(公告)日：2012-06-21

申请号：US13400967

申请日：2012-02-21

Applicant: Seung-Joon AHN ,  Jong-Chern Lee

Inventor： Seung-Joon AHN ,  Jong-Chern Lee

IPC: H03L7/08

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract translation: 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US08143925B2

公开(公告)日：2012-03-27

申请号：US12753442

申请日：2010-04-02

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03L7/06

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract translation: 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US08946869B2

公开(公告)日：2015-02-03

申请号：US13041003

申请日：2011-03-04

Applicant: Dae-Suk Kim ,  Jong-Chern Lee ,  Chul Kim

Inventor： Dae-Suk Kim ,  Jong-Chern Lee ,  Chul Kim

IPC: H01L29/00 ,  H01L29/80 ,  H01L23/48 ,  H01L21/66 ,  G01R31/28 ,  H01L23/00

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  H01L23/481 ,  H01L24/05 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract translation: 在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。 集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流， 在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

公开(公告)号：US08436651B2

公开(公告)日：2013-05-07

申请号：US12624144

申请日：2009-11-23

Applicant: Hyun-Su Yoon ,  Jong-Chern Lee

Inventor： Hyun-Su Yoon ,  Jong-Chern Lee

IPC: G06F7/38

CPC classification number: H04L7/02 ,  H04L7/0045

Abstract: A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.

Abstract translation: 半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

公开(公告)号：US08107310B2

公开(公告)日：2012-01-31

申请号：US12650594

申请日：2009-12-31

Applicant: Dae-Suk Kim ,  Jong-Chern Lee

Inventor： Dae-Suk Kim ,  Jong-Chern Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

Abstract translation: 半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址， 刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

公开(公告)号：US20110272790A1

公开(公告)日：2011-11-10

申请号：US12833672

申请日：2010-07-09

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。