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    MEMORY DEVICES AND OPERATING METHODS THEREOF
    91.
    发明申请
    MEMORY DEVICES AND OPERATING METHODS THEREOF 有权

    公开(公告)号：US20250124969A1

    公开(公告)日：2025-04-17

    申请号：US18669633

    申请日：2024-05-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyoung Lee ,  Yeongwoo Kang ,  Yongjun Kim

    IPC: G11C11/4091 ,  G11C11/408

    Abstract: Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.

    HEAD-MOUNTED DISPLAY DEVICE AND METHOD FOR CONTROLLING THE SAME
    92.
    发明申请
    HEAD-MOUNTED DISPLAY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权

    公开(公告)号：US20250124829A1

    公开(公告)日：2025-04-17

    申请号：US18812633

    申请日：2024-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Keeeun CHOI ,  Joayoung LEE

    IPC: G09G3/00 ,  G06F3/01

    Abstract: A method performed by a head mounted display (HMD) device includes: determining a sleep onset preparation start time; and displaying, on a display, a sleep onset preparation screen to which a visual effect is applied, from the sleep onset preparation start time, in a stepwise manner during a sleep onset preparation time interval, where the visual effect that is applied in the stepwise manner comprises a visual effect of switching a virtual screen output through an entire display area of the display to a video see through (VST) screen, where the VST screen displays the virtual screen with a non-virtual screen as a background in the entire display area of the display, where the non-virtual screen is based on an image captured through a front camera, and where the virtual screen is based on content executed by the HMD device.

    SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES
    95.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES 有权

    公开(公告)号：US20250123983A1

    公开(公告)日：2025-04-17

    申请号：US18791405

    申请日：2024-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin GIM ,  Heekwon PARK ,  Jaemin JUNG ,  Changho CHOI ,  Yang Seok KI

    IPC: G06F13/40 ,  G06F13/42

    Abstract: An apparatus including a switch may include a first interface configured to communicate with at least one memory device, and a second interface configured to communicate with a first physical connector and a second physical connector, where the switch is configured to communicate with a device using the first physical connector using a memory access protocol. The second interface may be configured to communicate with a second device using the second physical connector using the memory access protocol. The apparatus may further include a second switch including a third interface configured to communicate with the at least one memory device, and a fourth interface configured to communicate with a third physical connector and a fourth physical connector, where the second switch may be configured to communicate with the device using the third physical connector using the memory access protocol.

    METHOD AND APPARATUS FOR OPTIMIZING PREFETCH PERFORMANCE OF STORAGE DEVICE
    97.
    发明申请
    METHOD AND APPARATUS FOR OPTIMIZING PREFETCH PERFORMANCE OF STORAGE DEVICE 有权

    公开(公告)号：US20250123943A1

    公开(公告)日：2025-04-17

    申请号：US18909171

    申请日：2024-10-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyong Oh ,  Byeonghui Kim ,  Seongho Roh ,  Hyeongyu Min ,  Hyunkyo Oh ,  Dongchan Lee ,  Hankyoo Lee ,  Kibeen Jung

    IPC: G06F11/34

    Abstract: Provided are a method and apparatus for optimizing prefetch performance of a storage device. The method of optimizing prefetch performance of a storage device includes receiving prefetch data from the storage device configured to process a workload based on a parameter, generating prefetch performance data for a plurality of combinations of block size and queue depth, based on the prefetch data, generating index data for evaluating the prefetch performance data, based on the prefetch performance data, updating the parameter to generate an updated parameter based on the index data, and transferring, to the storage device, the updated parameter, wherein the generating of the index data includes generating the index data by taking into account an inversion interval in which prefetch performance decreases with an increase in the block size or the queue depth.

    MEMORY CONTROLLER FOR COMMUNICATING MEMORY STATUS INFORMATION, MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER
    98.
    发明申请
    MEMORY CONTROLLER FOR COMMUNICATING MEMORY STATUS INFORMATION, MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER 有权

    公开(公告)号：US20250123755A1

    公开(公告)日：2025-04-17

    申请号：US18670908

    申请日：2024-05-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehyun KIM ,  Suhyun KIM ,  Ikkyun PARK ,  Hyunju YI

    IPC: G06F3/06

    Abstract: An embodiment of the method includes transferring a first read command corresponding to a first cell region of the memory device through a first channel, receiving first data, read from the first cell region, from the memory device through a second channel physically separated from the first channel, transferring a status information request command through the first channel, the status information request command request the transfer of status information about a second cell region of the memory device, receiving the status information about the second cell region from the memory device through the first channel, and transferring a second read command corresponding to the second cell region of the memory device through the first channel, at least a portion of a period in which the status information is received through the first channel overlaps a period where the first data is received through the second channel.

    MEMORY SYSTEM, METHOD, AND MEMORY DEVICE WITH OFFLOADING
    99.
    发明申请
    MEMORY SYSTEM, METHOD, AND MEMORY DEVICE WITH OFFLOADING 有权

    公开(公告)号：US20250123746A1

    公开(公告)日：2025-04-17

    申请号：US18814996

    申请日：2024-08-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEONGWOOK PARK

    IPC: G06F3/06

    Abstract: A memory system includes an external memory device and a first memory processing unit of a main memory device. The external memory device and a host may be disposed on different boards, and the external memory device may transfer compressed data to the host in response to a swap-in request from the host. The first memory processing unit and the host may be disposed on the same board. The first memory processing unit may load the compressed data, decompress the compressed data to obtain decompressed data, and store the decompressed data in a main memory of the main memory device.

    VOLTAGE REGULATOR, ELECTRONIC SYSTEM INCLUDING THE SAME, AND OPERATION METHOD THEREOF
    100.
    发明申请
    VOLTAGE REGULATOR, ELECTRONIC SYSTEM INCLUDING THE SAME, AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20250123645A1

    公开(公告)日：2025-04-17

    申请号：US18733152

    申请日：2024-06-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunghun CHO ,  Juri LEE

    IPC: G05F1/575

    Abstract: A voltage regulator configured to generate an output voltage includes a comparison unit configured to generate a second voltage based on a reference voltage and a first voltage generated by a feedback of the output voltage, a power noise replica buffer unit configured to generate a third voltage including a power noise copied based on the second voltage, and a pass transistor configured to generate the output voltage in response to the third voltage.

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