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公开(公告)号：US20080229271A1
公开(公告)日：2008-09-18
申请号：US12126951
申请日：2008-05-26
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译： 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。
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公开(公告)号：US07395517B2
公开(公告)日：2008-07-01
申请号：US11230956
申请日：2005-09-20
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译： 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。
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公开(公告)号：US07376809B2
公开(公告)日：2008-05-20
申请号：US11076218
申请日：2005-03-09
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。
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94.发明授权公开(公告)号：US07327759B2
公开(公告)日：2008-02-05
申请号：US09912781
申请日：2001-07-25
IPC分类号： H04J3/24
CPC分类号： H04L49/9094 , H04L47/10 , H04L47/34 , H04L49/90 , H04L49/9089
摘要： Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.
摘要翻译： 数据包或数据帧可以在通过因特网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。 本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。 这通过将帧接收到用于处理的输入缓冲器中来实现。 与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。 仲裁员将每个帧分配给处理核心引擎。 输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。 保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。
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公开(公告)号：US06642865B2
公开(公告)日：2003-11-04
申请号：US10095489
申请日：2002-03-12
IPC分类号： H03M700
摘要： Described is a scalable interface including a plurality of 2-bit transmission channels. An encoder partitions a digital bit stream into 3 bits which are coded into 4 bits with each pair of bits in each 4 bit pattern transmitted via back-to-back clock cycles on separate ones of the channels.
摘要翻译： 描述了包括多个2位传输信道的可缩放接口。 编码器将数字比特流分割成3比特，其编码为4比特，每个4比特模式中的每对比特通过背对背时钟周期在单独的信道上发送。
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公开(公告)号：US07054855B2
公开(公告)日：2006-05-30
申请号：US09898253
申请日：2001-07-03
申请人： Claude Basso , Jean Louis Calvignac , Philippe Damon , Gordon Taylor Davis , Marco C. Heddes , Clark Debs Jeffries
发明人： Claude Basso , Jean Louis Calvignac , Philippe Damon , Gordon Taylor Davis , Marco C. Heddes , Clark Debs Jeffries
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , H04L29/12132 , H04L29/12594 , H04L61/1552 , H04L61/30 , Y10S707/99933 , Y10S707/99942
摘要： A method and system for performing a pattern match search for a data string having a plurality of characters separated by delimiters. In accordance with the method of the present invention a search key is constructed by generating a full match search increment comprising the binary representation of a data string element, wherein the data string element comprises all characters between a pair of delimiters. The search key is completed by concatenating a pattern search prefix to the full match search increment, wherein the pattern search prefix is a cumulative pattern search result of each previous full match search increment. A full match search is then performed within a lookup table utilizing the search key. In response to finding a matching pattern within the lookup table, the process returns to constructing a next search key. In response to not finding a matching pattern, the previous full match search result is utilized to process the data string.
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97.发明授权Network processor with single interface supporting tree search engine and CAM 失效具有单界面支持树搜索引擎和CAM的网络处理器公开(公告)号：US07953077B2
公开(公告)日：2011-05-31
申请号：US11457952
申请日：2006-07-17
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , G11C15/00 , H04L45/745 , H04L45/7453 , H04L49/90
摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.
摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。
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98.发明授权公开(公告)号：US06714562B1
公开(公告)日：2004-03-30
申请号：US09522369
申请日：2000-03-10
IPC分类号： H04J324
CPC分类号： H04L12/5601 , H04L2012/5657 , H04L2012/5658
摘要： Method and apparatus for segmenting variable length frames into fixed length cells in a network equipment. The method allows preparing information to build the cells resulting in the segmenting of a succession of frames directed to the same destination in said network equipment. The cell may be packed with more than one frame. The cell information comprises the address where to read the frame data in a first storage unit, the cell header itself which indicates if the cell includes data from one packet or for more packets, a pointer per each of said more packets, designating the place of the end of data of the previous packet in the cell and a cell type field indicating one of the following types: a start of a new frame type, a continuation of frame type, a end of current frame type and a start and a end of a new frame type. The segmenting apparatus comprises a finite state machine using an Add/substract unit to compute the cell information and write said cell information in a second storage unit.
摘要翻译： 用于将可变长度帧分割成网络设备中的固定长度单元的方法和装置。 该方法允许准备信息以构建小区，从而导致在所述网络设备中定向到同一目的地的一系列帧的分段。 电池可以包装多于一个框架。 小区信息包括在第一存储单元中读取帧数据的地址，指示小区是否包括来自一个分组的数据或更多分组的小区头自身，每个更多分组的指针，指定每个分组的位置 小区中的先前分组的数据的结束以及指示以下类型之一的小区类型字段：新帧类型的开始，帧类型的继续，当前帧类型的结束以及开始和结束 一种新的帧类型。 分割装置包括使用加/减单元计算单元信息并在第二存储单元中写入所述单元信息的有限状态机。
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99.发明授权Network processor with single interface supporting tree search engine and CAM 失效具有单界面支持树搜索引擎和CAM的网络处理器公开(公告)号：US07167471B2
公开(公告)日：2007-01-23
申请号：US09940758
申请日：2001-08-28
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , G11C15/00 , H04L45/745 , H04L45/7453 , H04L49/90
摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.
摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。
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公开(公告)号：US20080253398A1
公开(公告)日：2008-10-16
申请号：US12144195
申请日：2008-06-23
IPC分类号： H04J3/24
CPC分类号： H04L49/602 , H04L49/354 , H04L49/604 , H04L69/22
摘要： A method and structure is disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiple of such dispatch messages are bundled into a single composite dispatch message. Thus selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.
摘要翻译： 公开了一种用于将适当数据发送到网络处理系统的方法和结构，该网络处理系统包括用于提取网络处理器使用的协议报头字段的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 多个这样的分派消息被捆绑成单个复合调度消息。 因此，来自N个分组的所选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以指导入队， 在N个数据包的束上进行帧改变。
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