公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

Applicant: Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

Inventor： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC: G11C11/34 ,  H01L21/36

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract translation: 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07242622B2

公开(公告)日：2007-07-10

申请号：US11359044

申请日：2006-02-22

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: G11C16/04

CPC classification number: G11C16/0475

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

Abstract translation: 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US20070133307A1

公开(公告)日：2007-06-14

申请号：US11359044

申请日：2006-02-22

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: G11C16/04

CPC classification number: G11C16/0475

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

公开(公告)号：US20070120160A1

公开(公告)日：2007-05-31

申请号：US11627883

申请日：2007-01-26

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC: H01L31/113

CPC classification number: H01L27/14689 ,  H01L27/1463

Abstract: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

Abstract translation: 提供半导体器件及其制造方法。 在一个示例中，该方法包括在嵌入基板中的传感器上形成具有第一折射率的隔离结构。 在隔离结构上形成具有与第一折射率不同的第二折射率的第一层。 从隔离结构的至少一部分去除第一层。 在去除第一层之后，在隔离结构上形成具有第三折射率的第二层。 第三折射率基本上类似于第一折射率。

公开(公告)号：US20060276014A1

公开(公告)日：2006-12-07

申请号：US11146033

申请日：2005-06-07

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

IPC: H01L21/425 ,  H01L21/22

CPC classification number: H01L27/14689 ,  H01L27/14601 ,  H01L27/14643 ,  H01L29/66659 ,  H01L29/7834

Abstract: A self-aligned high-energy implantation process of forming a deep junction structure. For exposing a predetermined region of a semiconductor substrate, a masking structure has a gate layer, a hard mask layer patterned on the gate layer, and a photoresist layer covering parts of said semiconductor substrate, said gate layer and said hard mask layer. The hard mask layer has a thickness greater than 350 Angstroms. Using the masking structure and performing an ion implantation process requiring an energy greater than 70 keV, a doped region of a second conductive type is formed in the predetermined region of the semiconductor substrate of a first conductive type.

Abstract translation: 形成深结结构的自对准高能注入工艺。 为了暴露半导体衬底的预定区域，掩模结构具有栅极层，在栅极层上图案化的硬掩模层以及覆盖所述半导体衬底，所述栅极层和所述硬掩模层的部分的光致抗蚀剂层。 硬掩模层的厚度大于350埃。 使用掩模结构并执行需要大于70keV的能量的离子注入工艺，在第一导电类型的半导体衬底的预定区域中形成第二导电类型的掺杂区域。

公开(公告)号：US20060131634A1

公开(公告)日：2006-06-22

申请号：US10905194

申请日：2004-12-21

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792

Abstract: A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

Abstract translation: 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

公开(公告)号：US20060081898A1

公开(公告)日：2006-04-20

申请号：US10966641

申请日：2004-10-15

Applicant: Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu

IPC: H01L31/113

CPC classification number: H01L27/14621 ,  H01L27/14623

Abstract: A semiconductor device including a substrate having a plurality of image sensing elements formed therein, a plurality of spaced apart color filters overlying the substrate and a light blocking material interposed between adjacent spaced apart color filters.

Abstract translation: 一种半导体器件，包括其上形成有多个图像感测元件的衬底，覆盖在衬底上的多个间隔开的滤色器以及插入在相邻间隔开的滤色器之间的遮光材料。

公开(公告)号：US20060057765A1

公开(公告)日：2006-03-16

申请号：US10939894

申请日：2004-09-13

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

IPC: H01L21/00

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625

Abstract: A device includes an image sensing element. The device also includes a Silicon Dioxide (SiO2) layer, located over the image sensing element, exhibiting a first index of refraction. The device further includes a first lens, located over the SiO2 layer, exhibiting a second index of refraction greater than the first index of refraction. The device still further includes a color filter located over the first lens and a second lens located over the color filter.

Abstract translation: 一种装置包括图像感测元件。 该装置还包括位于图像感测元件上方的呈现第一折射率的二氧化硅（SiO 2）层。 该器件还包括位于SiO 2层之上的第一透镜，其具有大于第一折射率的第二折射率。 该装置还包括位于第一透镜上方的滤色器和位于滤色器上方的第二透镜。

公开(公告)号：US20050124116A1

公开(公告)日：2005-06-09

申请号：US10728767

申请日：2003-12-08

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

IPC: H01L21/336 ,  H01L27/06 ,  H01L31/113

CPC classification number: H01L27/0688

Abstract: A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.

Abstract translation: 至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质 层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。 隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。 介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。 位线从顶视图与字线重叠，以形成大致为十字形的形状。 通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。 第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

公开(公告)号：US09246015B2

公开(公告)日：2016-01-26

申请号：US12892044

申请日：2010-09-28

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

Abstract: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Abstract translation: 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。