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91.发明授权公开(公告)号：US07120630B2
公开(公告)日：2006-10-10
申请号：US10650397
申请日：2003-08-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.
摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。
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公开(公告)号：US06987760B2
公开(公告)日：2006-01-17
申请号：US09838395
申请日：2001-04-19
申请人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
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公开(公告)号：US06977928B1
公开(公告)日：2005-12-20
申请号：US09548906
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
CPC分类号： H04L12/18
摘要： A system and method of transmitting multiple output messages from a single input message system where the system is keeping the messages in order by correlating the output messages with the input messages. For each output message, an indicator is associated with the output message indicating whether this output message is the last message being generated for the given input message. This allows multicasting to occur in a system where the output is matched to the input by allowing multiple output messages to be associated with a single input message.
摘要翻译： 从单个输入消息系统发送多个输出消息的系统和方法，其中系统通过将输出消息与输入消息相关联来保持消息的顺序。 对于每个输出消息，指示符与输出消息相关联，指示该输出消息是否是针对给定输入消息生成的最后消息。 这允许在通过允许多个输出消息与单个输入消息相关联的输出与输入匹配的系统中发生多播。
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公开(公告)号：US06681340B2
公开(公告)日：2004-01-20
申请号：US09792533
申请日：2001-02-23
IPC分类号： G06F1110
CPC分类号： H04L1/0043 , H04L1/0063
摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.
摘要翻译： 一种用于有效实施纠错码方案的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 数据帧可以与帧控制块相关联。 处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。 处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。 与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。 第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。
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公开(公告)号：US06671280B1
公开(公告)日：2003-12-30
申请号：US09535794
申请日：2000-03-29
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L49/30 , H04L45/502 , H04L49/201 , H04L49/251 , H04L49/3009 , H04L49/602 , H04L49/606 , H04L2012/5618 , H04L2012/5665
摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.
摘要翻译： 公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。 电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。 最初在上行处理装置处接收输入流作为基于帧的流。 输入流可以被表征为属于具有基于帧的流和ATM流的组。 响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。 然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。
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公开(公告)号：US06658546B2
公开(公告)日：2003-12-02
申请号：US09792557
申请日：2001-02-23
IPC分类号： G06F1200
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9047
摘要： A method and system for reserving frame modification information in a data storage unit. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data. The processor may further comprise a data storage unit coupled to the data flow unit where the data storage unit comprises a plurality of buffers. The plurality of buffers is configured to store frames of data. A first buffer may be accessed to store the ending frame data of a first frame. A first bank in the first buffer stores the end of the first frame. A second bank in a second buffer may be reserved for storing frame modification information where the second bank corresponds to the first bank in the first buffer that stores the end of the first frame.
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公开(公告)号：US06642865B2
公开(公告)日：2003-11-04
申请号：US10095489
申请日：2002-03-12
IPC分类号： H03M700
摘要： Described is a scalable interface including a plurality of 2-bit transmission channels. An encoder partitions a digital bit stream into 3 bits which are coded into 4 bits with each pair of bits in each 4 bit pattern transmitted via back-to-back clock cycles on separate ones of the channels.
摘要翻译： 描述了包括多个2位传输信道的可缩放接口。 编码器将数字比特流分割成3比特，其编码为4比特，每个4比特模式中的每对比特通过背对背时钟周期在单独的信道上发送。
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公开(公告)号：US06557053B1
公开(公告)日：2003-04-29
申请号：US09477179
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F13/1673
摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.
摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。
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公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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100.发明授权Network processor which makes thread execution control decisions based on latency event lengths 失效基于延迟事件长度的线程执行控制决策的网络处理器公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译： 在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。 排队多个独立的指令执行线程使其能够快速访问共享存储器。 如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。 当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。 当短暂延迟事件完成时，控制返回到原始线程。 每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。 线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。
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