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91.发明授权Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same 有权具有长度为64800和码率为2/15和16符号映射的低密度奇偶校验码字的位交织器，以及使用相同位的比特交织方法公开(公告)号：US09577674B2
公开(公告)日：2017-02-21
申请号：US14626169
申请日：2015-02-19
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
Abstract translation: 位交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于16符号映射的调制器。
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92.发明授权Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same 有权长度为64800，码率为3/15的低密度奇偶校验编码器，以及使用其的低密度奇偶校验编码方法公开(公告)号：US09525432B2
公开(公告)日：2016-12-20
申请号：US14496627
申请日：2014-09-25
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/1102 , H03M13/116 , H03M13/1185 , H04L1/0041 , H04L1/0057 , H04L1/0058
Abstract: A low density parity check (LDPC) encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 低密度奇偶校验（LDPC）编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800和码率为3/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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93.发明授权Method and apparatus for transmitting/receiving broadcasting-communication data 有权用于发送/接收广播通信数据的方法和装置公开(公告)号：US08989319B2
公开(公告)日：2015-03-24
申请号：US14174622
申请日：2014-02-06
Inventor： Sung-Ik Park , Hyoungsoo Lim , Heung-Mook Kim , Soo-In Lee
CPC classification number: H04H40/18 , H04B1/709 , H04L1/0041 , H04L1/0047 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L2001/0093 , H04W52/322
Abstract: A broadcasting-communication data receiving apparatus for receiving mixed signals including original signals and additional signals. The apparatus includes a receiver for receiving the mixed signals and outputting mixed signals of a predetermined band, a first demodulator for receiving the mixed signals of the predetermined band and generating baseband mixed signals, an original data generator for receiving the baseband mixed signals and generating original data, an original signal generator for receiving the original data and generating baseband original signals, a modulator for receiving the baseband original signals and generating original signals of a predetermined band, a subtractor for subtracting the original and mixed signals of the predetermined band to thereby generate additional signals of a predetermined band, a second demodulator for receiving the additional signals of the predetermined band and generating baseband additional signals, and an additional data generator for receiving the baseband additional signals and generating additional data.
Abstract translation: 一种用于接收包括原始信号和附加信号的混合信号的广播通信数据接收装置。 该装置包括用于接收混合信号并输出预定频带的混合信号的接收机，用于接收预定频带的混合信号并产生基带混合信号的第一解调器，用于接收基带混合信号并产生原始数据的原始数据发生器 数据，用于接收原始数据并产生基带原始信号的原始信号发生器，用于接收基带原始信号并产生预定频带的原始信号的调制器，用于减去预定频带的原始信号和混合信号的减法器，从而产生 预定频带的附加信号，用于接收预定频带的附加信号并产生基带附加信号的第二解调器，以及用于接收基带附加信号并产生附加数据的附加数据发生器。
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94.发明授权公开(公告)号：US12212642B2
公开(公告)日：2025-01-28
申请号：US18450004
申请日：2023-08-15
Inventor： Jae-Young Lee , Heung-Mook Kim , Sung-Ik Park , Sun-Hyoung Kwon
IPC: H04L69/324 , H04L1/00 , H04L5/00 , H04L69/323 , H04H60/07
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information shared by the core layer signal and the enhanced layer signal, using the time-interleaved signal.
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公开(公告)号：US12096459B2
公开(公告)日：2024-09-17
申请号：US18354251
申请日：2023-07-18
Inventor： Jae-Young Lee , Soon-Choul Kim , Sung-Ik Park , Heung-Mook Kim
CPC classification number: H04W72/30 , H04L12/1859 , H04L12/4633
Abstract: Disclosed herein are a method and apparatus of broadcast gateway signaling for channel bonding. The apparatus for broadcast gateway signaling includes an input formatting unit configured to generate baseband packets corresponding to channel bonding; and a stream partitioner configured to allocate the baseband packets to two or more RF channels of the channel bonding for generating an outer tunnel data stream, the outer tunnel data stream generated in different ways according to a plurality of operation modes for the channel bonding.
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Patent Agency Ranking
96.发明授权公开(公告)号：US12068756B2
公开(公告)日：2024-08-20
申请号：US18325364
申请日：2023-05-30
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/1102 , H03M13/116 , H03M13/2778 , H03M13/2903 , H03M13/618 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/2906
Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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公开(公告)号：US11923872B2
公开(公告)日：2024-03-05
申请号：US18309278
申请日：2023-04-28
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2757 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US11778639B2
公开(公告)日：2023-10-03
申请号：US17476578
申请日：2021-09-16
Inventor： Jae-Young Lee , Soon-Choul Kim , Sung-Ik Park , Heung-Mook Kim
CPC classification number: H04W72/30 , H04L12/1859 , H04L12/4633
Abstract: Disclosed herein are a method and apparatus of broadcast gateway signaling for channel bonding. The apparatus for broadcast gateway signaling includes an input formatting unit configured to generate baseband packets corresponding to channel bonding; and a stream partitioner configured to allocate the baseband packets to two or more RF channels of the channel bonding for generating an outer tunnel data stream, the outer tunnel data stream generated in different ways according to a plurality of operation modes for the channel bonding.
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公开(公告)号：US11750225B2
公开(公告)日：2023-09-05
申请号：US17176903
申请日：2021-02-16
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Heung-Mook Kim , Jae-Young Lee , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/6552
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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公开(公告)号：US11722244B2
公开(公告)日：2023-08-08
申请号：US17714279
申请日：2022-04-06
Inventor： Sun-Hyoung Kwon , Sung-Ik Park , Jae-Young Lee , Bo-Mi Lim , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H04L1/0041 , H04J99/00 , H04L1/009 , H04L1/0057 , H04L1/0071 , H04L1/0083
Abstract: An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the preamble includes a field indicating a start position of a first complete FEC block corresponding to each of physical layer pipes.
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