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公开(公告)号：US09214567B2
公开(公告)日：2015-12-15
申请号：US14020096
申请日：2013-09-06
Applicant: GLOBALFOUNDRIES INC.
Inventor： Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC: H01L21/44 , H01L29/786 , H01L23/62 , H01L27/02
CPC classification number: H01L23/5256 , H01L23/5329 , H01L23/62 , H01L27/0288 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66742 , H01L29/78696 , H01L2924/0002 , H01L2924/00
Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.
Abstract translation: 在半导体衬底的一个区域中设置电熔丝。 电子熔断器包括从底部到顶部的基底金属半导体合金部分，第一金属半导体合金部分，第二金属半导体部分，第三金属半导体合金部分和第四金属半导体合金部分的垂直堆叠，其中 第一金属半导体合金部分和第三金属半导体部分具有垂直偏移并且不延伸超过第二金属半导体合金部分和第四金属半导体合金部分的垂直边缘的外边缘。
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公开(公告)号：US09190487B2
公开(公告)日：2015-11-17
申请号：US14283409
申请日：2014-05-21
Inventor： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
CPC classification number: H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。
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公开(公告)号：US20140256106A1
公开(公告)日：2014-09-11
申请号：US14283409
申请日：2014-05-21
Inventor： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
IPC: H01L29/66
CPC classification number: H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
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