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公开(公告)号：US20140124840A1
公开(公告)日：2014-05-08
申请号：US13670674
申请日：2012-11-07
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
IPC分类号： H01L29/78 , H01L21/336 , H01L21/311
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
摘要翻译： 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。
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公开(公告)号：US08809920B2
公开(公告)日：2014-08-19
申请号：US13670674
申请日：2012-11-07
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
摘要翻译： 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。
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公开(公告)号：US09190487B2
公开(公告)日：2015-11-17
申请号：US14283409
申请日：2014-05-21
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
摘要翻译： 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。
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公开(公告)号：US20140256106A1
公开(公告)日：2014-09-11
申请号：US14283409
申请日：2014-05-21
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Shom Ponoth , Alexander Reznicek , Raghavasimhan Sreenivasan , Xiuyu Cai , Ruilong Xie
IPC分类号： H01L29/66
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
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公开(公告)号：US09508851B2
公开(公告)日：2016-11-29
申请号：US14029198
申请日：2013-09-17
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure.
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公开(公告)号：US09070771B2
公开(公告)日：2015-06-30
申请号：US14460921
申请日：2014-08-15
IPC分类号： H01L29/78 , H01L29/06 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/10
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/66795
摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层 ，其中所述第二电介质层是高k电介质。 通过材料堆叠形成开口以暴露半导体衬底的表面。 通过材料堆叠在开口中形成半导体材料。 第一电介质层被选择性地去除到第二电介质层和半导体材料。 栅极结构形成在半导体材料的沟道部分上。 在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。
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公开(公告)号：US09034741B2
公开(公告)日：2015-05-19
申请号：US13906644
申请日：2013-05-31
发明人： Thomas N. Adam , Keith E. Fogel , Judson R. Holt , Balasubramanian Pranatharthiharan , Alexander Reznicek
IPC分类号： H01L21/425 , H01L29/66 , H01L21/02 , H01L29/78
CPC分类号： H01L29/086 , H01L21/0262 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/165 , H01L29/66492 , H01L29/66636 , H01L29/7816 , H01L29/7848
摘要： A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
摘要翻译： 一种半导体器件及其制造方法，其中该方法包括制造场效应晶体管（FET）。 该方法包括在半导体衬底内的多个σ形源极和漏极凹槽内生长掺杂的外延晕区域。 外延应力材料生长在由形成掺杂的外延卤素形成源和漏极区域所围绕的σ形源极和漏极区域中，并且具有受限的电流耗尽朝向沟道区域以提高器件性能。 外延区域的选择性生长允许控制掺杂物分布，并因此调节和增强器件内的载流子迁移率。
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8.发明申请EPITAXIAL SEMICONDUCTOR RESISTOR WITH SEMICONDUCTOR STRUCTURES ON SAME SUBSTRATE 有权具有相同基板上的半导体结构的外延半导体电阻公开(公告)号：US20150054081A1
公开(公告)日：2015-02-26
申请号：US14526767
申请日：2014-10-29
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/13 , H01L28/20 , H01L29/0649 , H01L29/36 , H01L29/41783
摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要翻译： 提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。 衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。 半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。 与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。 外延半导体电阻存在于电阻器件区域中。 从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基底半导体层的热通路。 未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。
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9.发明申请Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer 有权引起源/漏极和栅极部分与介质垫片或空气间隙垫片公开(公告)号：US20140327054A1
公开(公告)日：2014-11-06
申请号：US13875361
申请日：2013-05-02
CPC分类号： H01L29/41783 , H01L21/283 , H01L29/045 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/4991 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/7834
摘要： A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer.
摘要翻译： 提供半导体结构及其制造方法。 半导体器件包括通过选择性外延生长在半导体衬底的表面上形成的外延凸起的源极/漏极（RSD）区域。 在一个实施例中，RSD区域的小面侧部分被用于形成可以用电介质材料填充以形成电介质间隔区的空腔区域。 间隔物可以形成在电介质间隔区上。 在另一个实施例中，可以选择性地生长小面侧部分以在空腔区域中形成气隙间隔区域。 可以在空腔区域中形成具有内表面和外表面的共形间隔层，从而产生由保形间隔层的内表面限定的气隙间隔物。
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公开(公告)号：US20140312419A1
公开(公告)日：2014-10-23
申请号：US13865519
申请日：2013-04-18
发明人： Thomas N. Adam , Veeraraghavan S. Basker , Jinghong Li , Chung-Hsun Lin , Sebastian Naczas , Alexander Reznicek , Tenko Yamashita
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785 , H01L29/7853
摘要： A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.
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