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143 条记录 (耗时 0.029 秒)

    Dual-gate transistor device and method of forming a dual-gate transistor device
    93.
    发明授权
    Dual-gate transistor device and method of forming a dual-gate transistor device 有权
    双栅极晶体管器件和形成双栅极晶体管器件的方法

    公开(公告)号：US07064036B2

    公开(公告)日：2006-06-20

    申请号：US10932192

    申请日：2004-09-01

    申请人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

    发明人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

    摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.

    摘要翻译： 根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。 这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。 绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

    Silicon on insulator DRAM process utilizing both fully and partially depleted devices
    94.
    发明授权
    Silicon on insulator DRAM process utilizing both fully and partially depleted devices 有权
    使用完全和部分耗尽的器件的绝缘体上硅DRAM工艺

    公开(公告)号：US06818496B2

    公开(公告)日：2004-11-16

    申请号：US10265426

    申请日：2002-10-07

    申请人： Charles H. Dennison ,  John K. Zahurak

    发明人： Charles H. Dennison ,  John K. Zahurak

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/84 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/1203

    摘要： This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

    摘要翻译： 本发明涉及半导体集成电路领域，特别涉及制造在绝缘体上硅（SOI）衬底和器件上的独立和嵌入式存储器芯片。 部分耗尽（PD）和完全耗尽（FD）器件在同一芯片上被利用。 本发明是在芯片的一个区域中利用完全耗尽的SOI器件和在芯片的选定其他区域中部分耗尽的SOI器件的工艺流程。 完全耗尽或部分耗尽的选择仅由芯片的该特定区域中的电路应用决定。 本发明能够根据DRAM处理，特别是具有大比例的相关逻辑电路的嵌入式DRAM。

    Semiconductor construction of a trench
    95.
    发明授权
    Semiconductor construction of a trench 有权
    半导体构造的沟槽

    公开(公告)号：US06710420B2

    公开(公告)日：2004-03-23

    申请号：US10241923

    申请日：2002-09-11

    申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

    发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

    摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

    摘要翻译： 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

    SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY
    96.
    发明授权
    SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY 有权
    形成集成电路存储器件的半导体处理方法，形成电容器容器的方法，与电路电气连接的方法和相关集成电路

    公开(公告)号：US06611018B2

    公开(公告)日：2003-08-26

    申请号：US10209269

    申请日：2002-07-30

    申请人： Richard H. Lane ,  John K. Zahurak

    发明人： Richard H. Lane ,  John K. Zahurak

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/1052 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

    摘要： In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to one aspect of this implementation, the conductive layer is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide.

    摘要翻译： 一方面，本发明提供一种形成集成电路存储器件的方法。 在一个实现中，在存储器阵列区域和外围电路区域上形成导电层。 在导电层上形成难熔金属层，以在两个区域提供导电结构。 根据该实施方案的一个方面，导电层形成在存储器阵列之上，为要形成的电容器容器提供电接触。 根据该实施方案的另一方面，形成在外围电路区域上的导电层构成包括硅化物中的至少一些的导电线。

    Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures
    98.
    发明授权
    Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 有权
    电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法

    公开(公告)号：US06500709B2

    公开(公告)日：2002-12-31

    申请号：US09767480

    申请日：2001-01-22

    申请人： Kunal R. Parekh ,  John K. Zahurak

    发明人： Kunal R. Parekh ,  John K. Zahurak

    IPC分类号： H01L218242

    CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

    摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.

    摘要翻译： 本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。 本发明包括一种形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。 本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

    Method of improving static refresh
    99.
    发明授权
    Method of improving static refresh 有权
    改善静态刷新的方法

    公开(公告)号：US06482707B1

    公开(公告)日：2002-11-19

    申请号：US09532094

    申请日：2000-03-21

    申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

    发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/6656

    摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

    摘要翻译： 公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。 该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。 第一次毯式离子注入工艺具有第一能级和剂量。 该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。 在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。 第二次毯子离子注入过程具有第二能量水平和剂量。 所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。 此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

    Structure for improving static refresh
    100.
    发明授权
    Structure for improving static refresh 有权

    公开(公告)号：US06410951B1

    公开(公告)日：2002-06-25

    申请号：US09822249

    申请日：2001-04-02

    申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

    发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

    IPC分类号： H01L21336

    摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.