公开(公告)号：US08148225B2

公开(公告)日：2012-04-03

申请号：US12401555

申请日：2009-03-10

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07517743B2

公开(公告)日：2009-04-14

申请号：US11588274

申请日：2006-10-27

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07465999B2

公开(公告)日：2008-12-16

申请号：US10303696

申请日：2002-11-26

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L27/105 ,  H01L27/12

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US20090176338A1

公开(公告)日：2009-07-09

申请号：US12401555

申请日：2009-03-10

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07189606B2

公开(公告)日：2007-03-13

申请号：US10161615

申请日：2002-06-05

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/8238

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07151303B2

公开(公告)日：2006-12-19

申请号：US10751443

申请日：2004-01-06

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L27/105 ,  H01L27/12

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US09575727B2

公开(公告)日：2017-02-21

申请号：US14497777

申请日：2014-09-26

申请人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

发明人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

IPC分类号： G06F7/58 ,  G09C1/00 ,  G11C13/00 ,  H04L9/08 ,  H04L9/32

CPC分类号： G06F21/44 ,  G06F7/58 ,  G06F7/588 ,  G09C1/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

摘要翻译： 公开和描述了可操作以产生随机数的装置和系统。 这样包括电耦合到被配置为初始地将阵列中的所有单元设置为高状态的电路的相变材料单元的阵列，通过阵列发送编程脉冲，该阵列具有足以将每个单元随机地设置为高状态或 低状态以在阵列上产生单元状态的随机分布，并且读取阵列外的单元状态的随机分布。

公开(公告)号：US08273619B2

公开(公告)日：2012-09-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US20100297822A1

公开(公告)日：2010-11-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07767514B2

公开(公告)日：2010-08-03

申请号：US11406863

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。