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91.发明授权IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals 失效各种MLC（多级代码）信号的IPHD（迭代并行混合解码）公开(公告)号：US07383487B2
公开(公告)日：2008-06-03
申请号：US11017157
申请日：2004-12-20
CPC分类号： H04L1/005 , H03M13/1105 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/1148 , H03M13/255 , H03M13/258 , H03M13/2957 , H03M13/6325 , H03M13/658 , H04L1/0058 , H04L1/0071 , H04L27/18
摘要： IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.
摘要翻译： 各种MLC（多级码）信号的IPHD（迭代并行混合解码）。 提供了各种实施例，通过该实施例可以对使用多个映射映射的MLC LDPC（多级码低密度奇偶校验）编码的调制信号执行IPHD。 也可以对仅使用单个映射映射的MLC LDPC编码调制信号执行该IPHD。 此外，提供了可以在ML TC（多级Turbo码）信号上执行IPHD的各种实施例。 关于各种实施方案所示的IPHD的这些原理，MLC LDPC编码调制信号以及ML TC信号的IPHD也可以扩展到执行其他信号类型的IPHD。 一般而言，基于MLC信号的程度，相应数量的并行路径协同工作来解码MLC信号的各种级别。
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92.发明授权Inverse function of min*:min*- (inverse function of max*:max*-) 有权min *的反函数：min * - （最大*的反函数：max * - ）公开(公告)号：US07360146B1
公开(公告)日：2008-04-15
申请号：US10347732
申请日：2003-01-21
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/3922 , H03M13/395
摘要： Inverse function of min*:min*− (inverse function of max*:max*−). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*− (and/or inverse function of max*:max*−) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*− (and/or inverse function of max*:max*−) processing.
摘要翻译： min *的反函数：min * - （max *：max * - 的反函数）。 采用两个新参数来提供对于涉及从多个可能值中确定对数校正的最小值和/或对数校正最大值的代码进行大量改进的解码处理。 可以从由min *：min * - （和/或max *：max * - 的逆函数）提供的改进的解码处理中受益的一些代码的示例包括turbo编码，并行级联网格编码调制（ PC-TCM）码，turbo网格编码调制（TTCM）码和低密度奇偶校验（LDPC）码。 采用min *：min * - （和/或max *：max * - ）的逆函数处理的逆函数，信号解码中采用的处理步骤的总数显着减少。
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93.发明授权LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing 有权LDPC（低密度奇偶校验）编码信号解码使用并行和同时的比特节点和校验节点处理公开(公告)号：US07281192B2
公开(公告)日：2007-10-09
申请号：US10851614
申请日：2004-05-21
IPC分类号： H03M13/00
CPC分类号： H03M13/1137 , H04L1/005 , H04L1/0057
摘要： LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.
摘要翻译： LDPC（低密度奇偶校验）编码信号解码使用并行和同时的比特节点和校验节点处理。 这种LDPC编码信号的解码方法可以被描述为LDPC比特检验并行解码。 在一些替代实施例中，解码LDPC编码信号的方法可以被修改为LDPC符号校验并行解码或LDPC混合校验并行解码。 提出了一种新颖的方法，通过该方法，相对于校验节点的相对于位节点和边缘消息的边缘消息可以被同时并且彼此并行地更新。 适当构造的执行命令指示在两种节点类型（例如，边缘和检查）上更新边缘消息的同时操作的顺序。 对于包括并行块LDPC编码信号的各种类型的LDPC编码信号，该方法可以在几乎一半的时间内执行由先前的解码方法提供的解码处理。
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94.发明授权Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals 有权解码LDPC（低密度奇偶校验）编码信号和LDPC编码调制信号时的迭代度量更新公开(公告)号：US07216283B2
公开(公告)日：2007-05-08
申请号：US10669177
申请日：2003-09-23
CPC分类号： H04L1/006 , H03M13/1102 , H03M13/1105 , H03M13/1117 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H04L1/0041 , H04L1/005 , H04L1/0058 , H04L27/18 , H04L27/2602
摘要： Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.
摘要翻译： 解码LDPC（低密度奇偶校验）编码信号和LDPC编码调制信号时的迭代度量更新。 提出了一种新颖的方法来更新在执行LDPC编码信号的迭代解码时采用的比特量度。 该比特度量更新也适用于使用组合LDPC编码和调制编码生成的信号的解码，以生成LDPC编码调制信号。 此外，比特度量更新也可扩展到LDPC码可变码率和/或可变调制信号的解码，其码率和/或调制可以像逐个符号一样频繁地变化。 通过确保在迭代解码处理的各种迭代期间更新比特度量，可以比在迭代解码处理期间比特度量保持为固定值时更高的性能。
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公开(公告)号：US07159170B2
公开(公告)日：2007-01-02
申请号：US10668526
申请日：2003-09-23
CPC分类号： H04L27/2602 , G11B20/1833 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6516 , H03M13/6583 , H04L1/0041 , H04L1/005 , H04L1/0058 , H04L1/006 , H04L1/1671 , H04L27/18
摘要： LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.
摘要翻译： LDPC（低密度奇偶校验）编码调制符号解码。 通过适当地修改LDPC三部分图来消除比特节点从而生成LDPC二分图（使得符号节点被适当地映射到校验节点从而消除比特节点）来支持符号解码。 将符号节点通信地耦合到校验节点的边缘被适当地标记以支持LDPC编码调制信号的符号解码。 迭代解码处理可以包括更新校验节点以及估计符号序列和更新符号节点。 在一些实施例中，可以执行替代的混合解码方法，使得执行位电平和符号电平解码的组合。 该LDPC码解码仅执行比特解码。 此外，它提供可比较或更好的比特解码性能，涉及相关度量的迭代更新。
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96.发明授权公开(公告)号：US07017106B2
公开(公告)日：2006-03-21
申请号：US10901528
申请日：2004-07-29
IPC分类号： G06F11/00
CPC分类号： H04L1/005 , H04L1/0057
摘要： Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.
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公开(公告)号：US08473817B2
公开(公告)日：2013-06-25
申请号：US12632552
申请日：2009-12-07
申请人： Ba-Zhong Shen , Tak K. Lee , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Tak K. Lee , Kelly Brian Cameron
IPC分类号： H03M13/35
CPC分类号： H03M13/116 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362
摘要： LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.
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公开(公告)号：US08229039B2
公开(公告)日：2012-07-24
申请号：US12273506
申请日：2008-11-18
CPC分类号： H04L1/1835 , H03M13/09 , H03M13/2957 , H03M13/6306 , H04L1/0066 , H04L1/1819
摘要： Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
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公开(公告)号：US20090135965A1
公开(公告)日：2009-05-28
申请号：US12273506
申请日：2008-11-18
IPC分类号： H04L27/06
CPC分类号： H04L1/1835 , H03M13/09 , H03M13/2957 , H03M13/6306 , H04L1/0066 , H04L1/1819
摘要： Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
摘要翻译： 灵活的费率匹配。 在实现速率匹配时，对发送通信设备没有限制或限制。 接收通信设备能够适应基本上任何大小的接收的传输（例如，直到包括所有系统位和全部奇偶校验位的整个turbo码字）。 接收通信设备采用相对较小尺寸的存储器来确保较低成本，较小尺寸的通信设备（例如，手机或诸如个人无线通信设备的用户设备）。 此外，实现增量冗余，其中连续传输不需要包括其中的重复信息（例如，第二传输不需要包括来自第一传输的任何重复信息）。 只有到达要发送的比特或码字块的结束时，并且当在这种比特位块或码字的结尾发生环绕时，才会在稍后的传输中产生比特重复。
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公开(公告)号：US08408475B2
公开(公告)日：2013-04-02
申请号：US13555415
申请日：2012-07-23
CPC分类号： H04L1/1835 , H03M13/09 , H03M13/2957 , H03M13/6306 , H04L1/0066 , H04L1/1819
摘要： Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.
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