公开(公告)号：US07409006B2

公开(公告)日：2008-08-05

申请号：US11481365

申请日：2006-07-05

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

IPC分类号： H04L27/00

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US07360146B1

公开(公告)日：2008-04-15

申请号：US10347732

申请日：2003-01-21

申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/3922 ,  H03M13/395

摘要： Inverse function of min*:min*− (inverse function of max*:max*−). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*− (and/or inverse function of max*:max*−) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*− (and/or inverse function of max*:max*−) processing.

摘要翻译： min *的反函数：min * - （max *：max * - 的反函数）。 采用两个新参数来提供对于涉及从多个可能值中确定对数校正的最小值和/或对数校正最大值的代码进行大量改进的解码处理。 可以从由min *：min * - （和/或max *：max * - 的逆函数）提供的改进的解码处理中受益的一些代码的示例包括turbo编码，并行级联网格编码调制（ PC-TCM）码，turbo网格编码调制（TTCM）码和低密度奇偶校验（LDPC）码。 采用min *：min * - （和/或max *：max * - ）的逆函数处理的逆函数，信号解码中采用的处理步骤的总数显着减少。

公开(公告)号：US07137059B2

公开(公告)日：2006-11-14

申请号：US10335702

申请日：2003-01-02

申请人： Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

IPC分类号： H03M13/03

CPC分类号： H03M13/3911 ,  H03M13/3905 ,  H03M13/395 ,  H04L1/005 ,  H04L1/0055

摘要： Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, logic circuitry employs the results of the 2 element comparisons the smallest (min) or largest (max) input. The max or min implementations may be employed as part of the max* and/or min* implementations. For max* and/or min* implementations, simultaneous calculation of appropriate values is performed while determining which input is the smallest or largest. Thereafter, the determination of which input is the smallest or largest is used to select the appropriate resultant value (of the values calculated) for max* and/or min*. Various degrees of precision are employed for the log correction values within the max* and/or min* implementations.

摘要翻译： 单阶段实现min *，max *，min和/或max以在软中断（SISO）解码器中执行状态度量计算。 这允许以非常有效，快速的方式计算状态度量。 执行最小或最大计算时，使用可用输入的2个元素组合进行比较。 随后，逻辑电路采用2元素比较最小（最小）或最大（最大）输入的结果。 max或min实现可以用作max *和/或min *实现的一部分。 对于max *和/或min *实现，在确定哪个输入是最小或最大的时候执行适当值的同时计算。 此后，使用哪个输入是最小或最大的确定来选择适用于max *和/或min *的合成结果值（所计算的值）。 对于max *和/或min *实现中的对数校正值，采用了不同的精度。

公开(公告)号：US07499503B2

公开(公告)日：2009-03-03

申请号：US11728519

申请日：2007-03-26

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

IPC分类号： H04L27/36

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US4821224A

公开(公告)日：1989-04-11

申请号：US926436

申请日：1986-11-03

申请人： Wentai Liu ,  William T. Krakow ,  Thomas A. Hughes, Jr.

发明人： Wentai Liu ,  William T. Krakow ,  Thomas A. Hughes, Jr.

IPC分类号： G06F17/14 ,  G06F15/332

CPC分类号： G06F17/142

摘要： A method and apparatus for rasterizing a two-dimensional fast Fourier transform of a size N.times.N using a pipelined butterfly computational unit with 2logN processors. The invention avoids the problems associated with transposing the matrix so that the data can be continuously driven into the arithmetic processors in a pipelined fashion. It is devised for realtime applications using raster scan or serial input and output devices.

摘要翻译： 一种使用具有2logN处理器的流水线蝶形计算单元光栅化尺寸N×N的二维快速傅里叶变换的方法和装置。 本发明避免了与转置矩阵相关的问题，使得可以以流水线的方式将数据连续地驱动到算术处理器中。 它是为使用光栅扫描或串行输入和输出设备的实时应用设计的。

公开(公告)号：US5229668A

公开(公告)日：1993-07-20

申请号：US857457

申请日：1992-03-25

申请人： Thomas A. Hughes, Jr. ,  Carl T. Gray ,  Wentai Liu ,  Ralph K. Cavin, III

发明人： Thomas A. Hughes, Jr. ,  Carl T. Gray ,  Wentai Liu ,  Ralph K. Cavin, III

IPC分类号： H03K5/00 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K2005/00195

摘要： A data signal may be sampled at high speed using a clock signal by propagating the data signal and the clock signal through a series of data and clock delay elements, respectively, and latching the corresponding delayed data and clock signals. The sampling speed is thereby controlled by the relative skew between the clock and data signals, which can be made relatively small and may be limited only by noise and random variations in fabrication. Accordingly, high speed sampling may be obtained.

摘要翻译： 通过分别通过一系列数据和时钟延迟元件传播数据信号和时钟信号，并且锁存相应的延迟数据和时钟信号，可以使用时钟信号高速采样数据信号。 因此，采样速度由时钟和数据信号之间的相对偏移控制，时钟和数据信号之间的相对偏差可以做得相对较小，并且可以仅由噪声和制造中的随机变化来限制。 因此，可以获得高速采样。