公开(公告)号：US20210218954A1

公开(公告)日：2021-07-15

申请号：US17252843

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Ximin Zhang ,  Jill Boyce ,  Sang-Hee Lee ,  Scott Janus ,  Yunbiao Lin

IPC: H04N19/102 ,  H04N19/146

Abstract: Embodiments are generally directed to transport controlled video coding. An embodiment of an apparatus includes one or more processors to process data; a memory to store data, including data for video streaming; and a video processing mechanism including an encoder and a transport mechanism, wherein the video processing mechanism is to generate a prediction of channel throughput for a network channel, encode one or more bitstreams based on the prediction, including encoding a plurality of bitstreams including a first bitstream and a second bitstream if the prediction indicates an increase or decrease in channel throughput and encoding a single bitstream if the prediction indicates a stable channel throughput; and select a bitstream of the one or more bitstreams for a current frame.

公开(公告)号：US10929948B2

公开(公告)日：2021-02-23

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.

公开(公告)号：US10911799B2

公开(公告)日：2021-02-02

申请号：US16050475

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Prasoonkumar Surti ,  Stanley Baran ,  Michael Apodaca ,  Srikanth Potluri ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Archie Sharma ,  Jeffrey Tripp ,  Jason Ross ,  Barnan Das

IPC: H04N21/435 ,  H04N21/235 ,  H04N21/845 ,  G06T15/00 ,  G06T15/80 ,  G06T15/50 ,  H04N21/2662

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode point cloud data, reconstruct the decoded point cloud data and fill one or more holes in reconstructed point cloud frame data using patch metadata included in the decoded point cloud data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US20200211152A1

公开(公告)日：2020-07-02

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.

公开(公告)号：US20200043121A1

公开(公告)日：2020-02-06

申请号：US16050431

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Sang-hee Lee ,  Scott Janus ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Srikanth Potluri ,  Atsuo Kuwahara ,  Kai Xiao ,  Jason Tanner ,  Gokcen Cilingir ,  Archie Sharma ,  Jeffrey Tripp ,  Jason Ross ,  Barnan Das

IPC: G06T1/20 ,  G06T7/20 ,  G06T15/00 ,  G06T5/20 ,  H04N19/517 ,  H04N19/523

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode occupancy map data and auxiliary patch information and generate a plurality of patch video frames based on patch data decoded from the occupancy map data and auxiliary patch information, and a memory communicatively coupled to the one or more processors.

公开(公告)号：US10402160B2

公开(公告)日：2019-09-03

申请号：US14928878

申请日：2015-10-30

Applicant: Intel Corporation

Inventor： Scott Janus

IPC: G06F3/048 ,  G06F3/16 ,  G09G3/00 ,  H04R1/00 ,  H04S7/00 ,  G06F3/14

Abstract: Techniques for improved audio localization for visual effects. In one embodiment, for example, an apparatus may comprise a processor circuit and an audio management module, and the audio management module may be operable by the processor circuit to determine a position of a user interface element in a presentation area, determine an audio effect corresponding to the user interface element, determine audio location information for the audio effect based on the position of the user interface element, the audio location information defining an apparent position for the audio effect, and generate audio playback information for the audio effect based on the audio location information.

公开(公告)号：US09519803B2

公开(公告)日：2016-12-13

申请号：US13690401

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Prashant Dewan ,  Uday R. Savagaonkar ,  David M. Durham ,  Paul S. Schmitz ,  Jason Martin ,  Michael Goldsmith ,  Ravi L. Sahita ,  Francis X. McKeen ,  Carlos Rozas ,  Balaji Vembu ,  Scott Janus ,  Geoffrey S. Strongin ,  Xiaozhu Kang ,  Karanvir S. Grewal ,  Siddhartha Chhabra ,  Alpha T. Narendra Trivedi

IPC: G06F21/00 ,  G06F21/64 ,  G06F21/53 ,  G06F21/56

CPC classification number: G06F21/64 ,  G06F21/53 ,  G06F21/56

Abstract: In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.

Abstract translation: 根据一些实施例，可以为图形处理单元定义受保护的执行环境。 该框架不仅保护了图形处理单元上运行的恶意软件的工作负载，还保护了这些工作负载免受中央处理单元上运行的恶意软件。 此外，信任框架可以通过测量用于执行工作负载的代码和数据结构来促进安全执行的证明。 如果该框架或受保护的执行环境的可信计算基础的一部分受到损害，那么该部分可以被远程修补，并且在一些实施例中可以通过验证远程验证修补。