公开(公告)号：US12229867B2

公开(公告)日：2025-02-18

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike MacPherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US12147302B2

公开(公告)日：2024-11-19

申请号：US17095530

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US12124533B2

公开(公告)日：2024-10-22

申请号：US17482875

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Scott Janus ,  Sungye Kim

IPC: G06F18/2136 ,  G06T11/00

CPC classification number: G06F18/2136 ,  G06T11/00 ,  G06T2207/20076 ,  G06T2207/20081

Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.

公开(公告)号：US12124383B2

公开(公告)日：2024-10-22

申请号：US17862739

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/123 ,  G06T1/60

CPC classification number: G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60 ,  G06F2212/302

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20240256456A1

公开(公告)日：2024-08-01

申请号：US18391346

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G06F12/0862 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/0862 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/602 ,  G06F2212/608

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20230351543A1

公开(公告)日：2023-11-02

申请号：US18310688

申请日：2023-05-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Valentin Andrei ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, JR. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06N3/084 ,  G06F15/80 ,  G06F17/16 ,  G06N3/048 ,  G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06F7/544 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06F7/5443 ,  G06F9/5027 ,  G06F12/0806 ,  G06F15/8046 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

公开(公告)号：US11676239B2

公开(公告)日：2023-06-13

申请号：US17303654

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06F7/544 ,  G06N3/04 ,  G06N3/08 ,  G06N3/084 ,  G06N3/048

CPC classification number: G06T1/20 ,  G06F7/5443 ,  G06F9/5027 ,  G06F12/0806 ,  G06F15/8046 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US20220138895A1

公开(公告)日：2022-05-05

申请号：US17430041

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Vasanth Raganathan ,  Abhishek R. Appu ,  Ben Ashbaugh ,  Peter Doyle ,  Brandon Fliflet ,  Arthur Hunter ,  Brent Insko ,  Scott Janus ,  Altug Koker ,  Aditya Navale ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  James Valerio

IPC: G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.

公开(公告)号：US11322099B2

公开(公告)日：2022-05-03

申请号：US16939916

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US11315304B2

公开(公告)日：2022-04-26

申请号：US17003011

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Alexey Supikov ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws ,  Michael Doyle

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.