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公开(公告)号：US20190042265A1
公开(公告)日：2019-02-07
申请号：US15665653
申请日：2017-08-01
摘要： Embodiments of the present invention include methods, systems, and computer program products for implementing wide vector execution in a single thread mode for an out-of-order processor. A non-limiting example of the computer-implemented method includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.
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公开(公告)号：US09910781B2
公开(公告)日：2018-03-06
申请号：US15383306
申请日：2016-12-19
IPC分类号： G06F12/0862 , G06F12/1009
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F12/0882 , G06F12/1009 , G06F2212/602 , G06F2212/65
摘要： Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.
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93.发明申请Data Compression Accelerator Methods, Apparatus and Design Structure with Improved Resource Utilization 有权数据压缩加速器方法，设备和设计结构，改善资源利用率公开(公告)号：US20160283398A1
公开(公告)日：2016-09-29
申请号：US14670605
申请日：2015-03-27
CPC分类号： G06F12/1018 , G06F5/065 , G06F2212/401 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/6058
摘要： Methods, apparatus and design structures are provided for improving resource utilization by data compression accelerators. An exemplary apparatus for compressing data comprises a plurality of hardware data compression accelerators and a hash table shared by the plurality of hardware data compression accelerators. Each of the plurality of hardware data compression accelerators optionally comprises a first-in-first-out buffer that stores one or more input phrases. The hash table optionally records a location in the first-in-first-out buffers where a previous instance of an input phrase is stored. The plurality of hardware data compression accelerators can simultaneously access the hash table. For example, the hash table optionally comprises a plurality of input ports for simultaneous access of the hash table by the plurality of hardware data compression accelerators. A design structure for a data compression accelerator system is also disclosed.
摘要翻译： 提供了方法，设备和设计结构，以提高数据压缩加速器的资源利用率。 用于压缩数据的示例性装置包括多个硬件数据压缩加速器和由多个硬件数据压缩加速器共享的哈希表。 多个硬件数据压缩加速器中的每一个可选地包括存储一个或多个输入短语的先进先出缓冲器。 散列表可选地在前进先出的缓冲器中记录一个位置，其中存储输入短语的先前实例。 多个硬件数据压缩加速器可以同时访问散列表。 例如，散列表可选地包括用于由多个硬件数据压缩加速器同时访问散列表的多个输入端口。 还公开了一种用于数据压缩加速器系统的设计结构。
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公开(公告)号：US20150293704A1
公开(公告)日：2015-10-15
申请号：US14253072
申请日：2014-04-15
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F12/0862 , G06F2212/251 , G06F2212/602
摘要： Embodiments relate to memory-area property storage including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application that is executed by a processor of a computer. Another aspect includes determining the data fetch width indicator for the allocated memory page. Another aspect includes setting the data fetch width indicator in the at least one memory-area property storage in the allocated memory page. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the allocated memory page: determining the data fetch width indicator in the memory-area property storage associated with the location of the address; and fetching an amount of data from the memory page based on the data fetch width indicator.
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公开(公告)号：US20150293703A1
公开(公告)日：2015-10-15
申请号：US14253059
申请日：2014-04-15
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F12/0882 , G06F12/1009 , G06F2212/602 , G06F2212/65
摘要： Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.
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