公开(公告)号：US09208714B2

公开(公告)日：2015-12-08

申请号：US13198657

申请日：2011-08-04

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/20

CPC分类号： G09G3/2007 ,  G09G2300/043 ,  G09G2300/0838 ,  G09G2300/0876 ,  G09G2310/04

摘要： A display panel is provided, including an image data storage capacitor, a capacitive element, and four switches. The image data storage capacitor stores an image data. The sample unit has a control terminal for receiving a sample control signal. The capacitive element has a first terminal coupled to a pixel electrode of the image data storage capacitor via the sample unit. The first refresh unit has a control terminal coupled to the first terminal. The second refresh unit has a control terminal for receiving a refresh control signal. The third and first refresh units are serially coupled with each other between a corresponding source line and the image data storage capacitor for receiving a data signal. The shunt unit has a control terminal coupled to the pixel electrode, a data terminal coupled to the first terminal, and another data terminal for receiving a shunt control signal.

摘要翻译： 提供了一种显示面板，包括图像数据存储电容器，电容元件和四个开关。 图像数据存储电容器存储图像数据。 采样单元具有用于接收采样控制信号的控制端。 电容元件具有通过采样单元耦合到图像数据存储电容器的像素电极的第一端子。 第一刷新单元具有耦合到第一端子的控制端子。 第二刷新单元具有用于接收刷新控制信号的控制终端。 第三和第一刷新单元在对应的源极线和用于接收数据信号的图像数据存储电容器之间彼此串联耦合。 分路单元具有耦合到像素电极的控制端子，耦合到第一端子的数据端子和用于接收分流控制信号的另一数据端子。

公开(公告)号：US09159283B2

公开(公告)日：2015-10-13

申请号：US13185126

申请日：2011-07-18

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3618 ,  G09G3/3648 ,  G09G2300/0465 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2300/0876

摘要： A switch circuit, a pixel element and a display panel are provided. The switch circuit is for the pixel element, and includes switches. A switch is turned on to perform a sample operation on the pixel element. Another switch has a control terminal coupled to an image data storage capacitor of the pixel element via the switch, a data terminal to a corresponding source line, and another data terminal to the image data storage capacitor. During the sample operation, the second switch stores an image data of the image data storage capacitor in a parasitic gate capacitor existing on its control terminal. The parasitic gate capacitor maintains its stored data from the sample operation to a refresh operation in which the pixel element is refreshed. The second switch selectively electrically connects its two data terminals with each other according to stored image data in the parasitic gate capacitor.

摘要翻译： 提供开关电路，像素元件和显示面板。 开关电路用于像素元件，并且包括开关。 打开开关以对像素元件执行采样操作。 另一个开关具有经由开关耦合到像素元件的图像数据存储电容器的控制端子，对应的源极线的数据端子和与图像数据存储电容器的另一数据端子耦合的控制端子。 在采样操作期间，第二开关将图像数据存储电容器的图像数据存储在其控制端子上存在的寄生栅极电容器中。 寄生栅极电容将其存储的数据从采样操作维持到刷新像素元件的刷新操作。 第二开关根据寄存栅极电容器中存储的图像数据选择性地将其两个数据端子彼此电连接。

公开(公告)号：US08866711B2

公开(公告)日：2014-10-21

申请号：US12716156

申请日：2010-03-02

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3618 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2330/021

摘要： A liquid crystal display device and a driving method thereof capable of reducing flicker are provided. During a predetermined time period, two continuous inversion operations to pixel voltages and common voltages are repeatedly performed with a timing interval in which the liquid crystal component does not react to changes. After the predetermined time period, the pixel voltages and common voltages are performed by a single inversion operation such that they are phase inverted. Then, the pixel voltages and common voltages are repeatedly performed during the predetermined period by two continuous inversion operations with the timing interval in which the liquid crystal component does not react to changes.

摘要翻译： 提供了能够减少闪烁的液晶显示装置及其驱动方法。 在预定时间段期间，以液晶组件不响应于变化的定时间隔重复执行对像素电压和公共电压的两次连续反转操作。 在预定时间段之后，像素电压和公共电压通过单次反转操作进行，使得它们被相位反转。 然后，通过两次连续的反转操作，在预定的周期内重复执行像素电压和公共电压，其中液晶组件不响应于变化的定时间隔。

公开(公告)号：US08508516B2

公开(公告)日：2013-08-13

申请号：US12572380

申请日：2009-10-02

申请人： Keitaro Yamashita ,  Yoshikazu Matsui

发明人： Keitaro Yamashita ,  Yoshikazu Matsui

IPC分类号： G09G3/34

CPC分类号： G09G3/3666 ,  G09G3/2074 ,  G09G3/3208 ,  G09G3/3659 ,  G09G2300/0804 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2310/027

摘要： A display device includes a plurality of pixels arranged in a matrix with columns and rows. A source driver provides either analogue or digital image data for the pixels. Each pixel includes a plurality of sub-pixels. Each sub-pixel includes a display components, a memory unit for memorizing gradation display data included in the digital image data provided by the source driver for the display component, and a data switching unit for switching data providing for the display component to either the gradation display data memorized in the memory unit or the analogue image data provided by the source driver.

摘要翻译： 显示装置包括以列和行排列成矩阵的多个像素。 源驱动器为像素提供模拟或数字图像数据。 每个像素包括多个子像素。 每个子像素包括显示组件，用于存储由用于显示组件的源驱动器提供的数字图像数据中包括的灰度显示数据的存储单元，以及用于将提供显示组件的数据切换到灰度级的数据切换单元 存储在存储器单元中的显示数据或由源驱动器提供的模拟图像数据。

公开(公告)号：US20120235979A1

公开(公告)日：2012-09-20

申请号：US13433073

申请日：2012-03-28

申请人： Minoru SHIBAZAKI ,  Keitaro Yamashita

发明人： Minoru SHIBAZAKI ,  Keitaro Yamashita

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3648 ,  G02F1/13624 ,  G09G2300/0456 ,  G09G2310/0262 ,  G09G2320/0233

摘要： This present invention provides a liquid crystal display (LCD) device in which the sub-pixel is provided with three different voltage levels, so that image quality is improved without the configuration of additional gate lines. The present invention overcomes the reduction of aperture ratio in conventional LCD devices due to the configuration of additional gate lines. By the present invention, the white washout problem relating to the off-axis viewing angle can be overcome while the aperture ratio is not reduced.

摘要翻译： 本发明提供了一种液晶显示（LCD）装置，其中子像素具有三个不同的电压电平，使得在没有附加栅极线的配置的情况下，图像质量得到改善。 由于附加栅极线的配置，本发明克服了常规LCD器件中的开口率的降低。 通过本发明，可以克服与轴向视角有关的白色冲洗问题，同时孔径比不降低。

公开(公告)号：US07940083B2

公开(公告)日：2011-05-10

申请号：US12177684

申请日：2008-07-22

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03L5/00

CPC分类号： H03K19/00384 ,  H03K19/018521 ,  H03K19/018528

摘要： A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source VH and the N-MOS transistor is connected to a low potential source VL. The gate of each MOS transistor is connected to an input signal line. The inverter circuit further includes a P-MOS transistor connected between a node and input signal line, and an N-MOS transistor connected between a node of the N-MOS transistors and the input signal line. The gates of the P-MOS transistor and the N-MOS transistor are connected to an output signal line of the inverter circuit.

摘要翻译： 一种半导体集成电路，其能够维持包括多个级联连接的晶体管的电路中的晶体管的特性。 电路包括具有P-MOS晶体管和一对N-MOS晶体管的串联连接的反相器。 P-MOS晶体管连接到高电位源VH，并且N-MOS晶体管连接到低电位源VL。 每个MOS晶体管的栅极连接到输入信号线。 逆变器电路还包括连接在节点和输入信号线之间的P-MOS晶体管，以及连接在N-MOS晶体管的节点和输入信号线之间的N-MOS晶体管。 P-MOS晶体管和N-MOS晶体管的栅极连接到逆变器电路的输出信号线。

公开(公告)号：US07928948B2

公开(公告)日：2011-04-19

申请号：US11659866

申请日：2005-08-11

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0213 ,  G09G2310/0224 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2330/021

摘要： The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.

摘要翻译： 本发明的目的是在减少功耗的同时防止伪影的发生。 用于交替驱动像素的矩阵寻址方法。 图像的帧周期通过在多个块周期的时间序列上连续排序形成，每个块周期由作为用于对一个像素电压的时间序列应用定时的连续排序的前半部分组成的第一半块组成 或更多的行电极被设置为一个极性，第二半块是用于对要被提供有另一极性的一个或多个行电极的像素电压的时间序列应用定时连续排序的周期。 在第一半块中选择偶数行电极和奇数行电极在显示屏上的排列顺序。 在下半部分中选择与空间相邻的那些。 在一个帧周期期间，前半个块中的行电极选择顺序和第二半块中的行电极选择顺序分别与在另一个帧周期期间的对应的半块中的阶数不同，以便减轻块周期 -base视觉伪影。

公开(公告)号：US07859508B2

公开(公告)日：2010-12-28

申请号：US11517317

申请日：2006-09-08

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184

摘要： A liquid crystal drive circuit in which the degradation of the element is minimized in partial drive even for the GOG circuit configured by amorphous silicon, and a liquid crystal display device including the same are provided. The liquid crystal driving circuit includes a first shift register and a driving means. The first shift register advances through the line address of a pixel array to display an image, and outputs an enable signal only to drive the display target line. The driving means outputs a line drive signal corresponding to the enable signal to drive the line enabled by the first shift register.

摘要翻译： 即使对于由非晶硅构成的GOG电路，元件的劣化最小化的液晶驱​​动电路和包括该液晶驱动电路的液晶显示装置也是如此。 液晶驱动电路包括第一移位寄存器和驱动装置。 第一移位寄存器前进通过像素阵列的行地址以显示图像，并且仅输出使能信号以驱动显示目标线。 驱动装置输出与使能信号相对应的线驱动信号，以驱动由第一移位寄存器使能的线。

公开(公告)号：US20090273388A1

公开(公告)日：2009-11-05

申请号：US12404112

申请日：2009-03-13

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： H03K17/62

CPC分类号： H03K17/693 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2310/0297 ,  H03K17/007

摘要： A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

摘要翻译： 解复用器包括用于提供输入信号的输入端子，用于输出输入信号的多个输出端子以及耦合在输入端子和多个输出端子之间的开关电路，并且从多个输出端选择性地输出输入信号 终端根据提供给多个控制终端的多个控制信号。 为了使多路分解器小型化，开关电路包括串联连接在输入端和每个输出端之间的一个或多个开关元件，其中响应一个控制信号同时切换耦合到不同输出端的至少两个开关元件 从多个控制终端。

公开(公告)号：US20090160842A1

公开(公告)日：2009-06-25

申请号：US12332751

申请日：2008-12-11

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G06F3/038

CPC分类号： G09G3/3677

摘要： A drive circuit is disclosed. The drive circuit includes a first p-typed thin film transistor (PTFT), a second PTFT, a first n-typed thin film transistor (NTFT), a second NTFT and a capacitor. The drain of the first PTFT is coupled to a first electrical line, and the gate thereof is coupled to a first clock line. The drain of the second PTFT is coupled to a second clock line, and the source thereof is coupled to an output. The source of the first NTFT is coupled to a second electrical line, and the gate thereof is couple to an output of a preceding drive circuit. The source of the second NTFT is couple to a third electrical line, the gate thereof is coupled to a third clock line, and the drain thereof is coupled to the output. The capacitor has one end coupled to the second electrical line, while the other end is coupled to the source of the first PTFT, the drain of the first NTFT and the gate of the second PTFT.

摘要翻译： 公开了一种驱动电路。 驱动电路包括第一p型薄膜晶体管（PTFT），第二PTFT，第一n型薄膜晶体管（NTFT），第二NTFT和电容器。 第一PTFT的漏极耦合到第一电线，并且其栅极耦合到第一时钟线。 第二PTFT的漏极耦合到第二时钟线，并且其源极耦合到输出端。 第一NTFT的源极耦合到第二电线，并且其栅极耦合到先前的驱动电路的输出端。 第二NTFT的源耦合到第三电线，其栅极耦合到第三时钟线，并且其漏极耦合到输出端。 电容器具有耦合到第二电线的一端，而另一端耦合到第一PTFT的源极，第一NTFT的漏极和第二PTFT的栅极。