公开(公告)号：US20100306470A1

公开(公告)日：2010-12-02

申请号：US12471652

申请日：2009-05-26

申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F13/1621 ,  G06F12/0811 ,  G06F12/0835

摘要： Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.

摘要翻译： 描述了有效的技术来实现存储器访问的顺序。 从未被配置为生成存储器障碍命令的设备接收到存储器访问请求。 响应于存储器访问请求产生替代屏障。 存储器访问请求可以是读请求。 在存储器写入请求的情况下，在写入请求被处理之前生成替代屏障。 替代障碍也可以响应于以与读取请求相同的地址的先前写入请求为条件的存储器读取请求而产生。 一致性在分层存储器系统中实施，就好像从设备接收到不产生存储器屏障命令的存储器屏障命令一样。

公开(公告)号：US20080281996A1

公开(公告)日：2008-11-13

申请号：US12179970

申请日：2008-07-25

申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

IPC分类号： G06F13/38 ,  G06F3/00

CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

公开(公告)号：US07421529B2

公开(公告)日：2008-09-02

申请号：US11254391

申请日：2005-10-20

申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Jaya Prakash Subramaniam Ganasan

发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Jaya Prakash Subramaniam Ganasan

IPC分类号： G06F12/14

CPC分类号： G06F9/526

摘要： Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

摘要翻译： 信号量操作管理对由多个处理元件共享的存储器的独占访问。 由处理元件独占访问的信号量预留状态由存储器控制器监视。 为了清除过时的预约状态，在禁止更新存储器的内容的同时，向存储器发送用于写入操作的命令信号。 响应于接收到命令信号，控制器的预约状态从预约状态改变为非预约状态。

公开(公告)号：US20080183967A1

公开(公告)日：2008-07-31

申请号：US11669245

申请日：2007-01-31

申请人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

发明人： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/128 ,  G06F2212/1028 ,  Y02D10/13

摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. When it is determined that displaced lines have already been allocated in a higher level, the allocations of the displaced cache lines are prevented in the next level cache, thus, reducing castouts. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.

摘要翻译： 技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 当确定已移位的行已经被分配在较高级别时，在下一级高速缓存中防止移位的高速缓存行的分配，从而减少转移。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。 防止所选线路的分配节省与分配相关联的功率。

公开(公告)号：US07376815B2

公开(公告)日：2008-05-20

申请号：US11066957

申请日：2005-02-25

申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F8/447 ,  G06F9/382

摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.

摘要翻译： 公开了用于确保指令串的同步预解码的技术。 指令串包含来自可变长度指令集和嵌入数据的指令。 一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。 该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。 在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

公开(公告)号：US07330941B2

公开(公告)日：2008-02-12

申请号：US11088383

申请日：2005-03-23

申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer

发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

摘要翻译： 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含修改后的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。 在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。

公开(公告)号：US06907502B2

公开(公告)日：2005-06-14

申请号：US10264169

申请日：2002-10-03

申请人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

发明人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Thomas Philip Speier ,  Barry Joe Wolford

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0831

摘要： A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.

摘要翻译： 一种用于将窥探优先级的方法推送到在请求FIFO内调度请求的数据处理系统中。 接收到的每个新请求被置于请求FIFO的最后位置，并且请求FIFO通常仅基于请求FIFO内的顺序授予请求。 由于先前请求被顺序授权，所以随后的请求更接近请求FIFO的第一位置。 然而，当在请求FIFO处接收到窥探推送时，窥探推送将自动插入请求FIFO的第一个位置，而在请求FIFO之前尚未被授予请求。

公开(公告)号：US06807608B2

公开(公告)日：2004-10-19

申请号：US10077560

申请日：2002-02-15

申请人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Barry Joe Wolford

发明人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Bernard Charles Drerup ,  Richard Gerard Hofmann ,  Thomas Andrew Sartorius ,  Barry Joe Wolford

IPC分类号： G06F1200

CPC分类号： G06F12/0831 ,  Y02D10/13

摘要： A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.

摘要翻译： 用于执行可变大小的存储器一致性事务的方法和系统。 耦合在从机和主机之间的总线接口单元可以被配置为从主机接收包括多个相干性颗粒的请求（主请求）。 系统中的每个窥探单元可以被配置为一次窥探主请求中的不同数量的一致性粒子。 一旦总线接口单元已经从每个窥探逻辑单元接收到指示集合的指示集合，指示主请求中的相关性集合的集合已被每个监听单元窥探，并且用于收集相关性颗粒的地址上的数据 被侦听未被更新，总线接口单元可以允许未更新的那些一致性粒度的地址上的数据在请求主机和从机之间传送。

公开(公告)号：US6001662A

公开(公告)日：1999-12-14

申请号：US982440

申请日：1997-12-02

申请人： Anthony Correale, Jr. ,  James Norris Dieffenderfer ,  Trevor Scott Garner ,  Ronald William Kohake ,  Ketan Vitthal Patel

发明人： Anthony Correale, Jr. ,  James Norris Dieffenderfer ,  Trevor Scott Garner ,  Ronald William Kohake ,  Ketan Vitthal Patel

IPC分类号： G05B19/418 ,  H01L21/00

CPC分类号： G05B19/41875 ,  G05B2219/33323 ,  Y02P90/14 ,  Y02P90/16 ,  Y02P90/22

摘要： A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.

摘要翻译： 一种用于制造具有嵌入其中的多个存储器单元的集成电路器件的方法和系统。 最初，在集成电路装置内制造单个可重复使用的可配置测试电路。 然后识别嵌入集成电路设备内的每个存储单元的数量和类型。 最后，单个可重复使用的可配置测试电路被配置为响应于每个存储器单元的数量和类型的识别，使得仅需要一个测试电路用于具有嵌入其中的多个不同存储器单元的多个集成电路器件。 单个可重复使用的可配置测试电路可以放置在集成电路器件的固定磁芯内或外部。 此外，单个可重复使用的可配置测试电路可以包括阵列内置自检（ABIST）控制器，其包括分层存储器配置，其包括状态机，地址计数器，比较寄存器和数据模式发生器。

公开(公告)号：US08527713B2

公开(公告)日：2013-09-03

申请号：US11343765

申请日：2006-01-31

申请人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F12/0888 ,  G06F9/30047 ,  G06F9/3824

摘要： A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from main memory in the event of a cache miss; however, these instructions are not allowed to allocate entries in the cache. Only the predetermined instructions (for example, those used to establish locked cache entries) may allocate entries in the cache. When the locked entries are established, the processor exits BNCA mode, and any memory access instruction may allocate cache entries. BNCA mode may be indicated by setting a bit in a configuration register.

摘要翻译： 为处理器定义块正常缓存分配（BNCA）模式。 在BNCA模式中，缓存条目只能通过预定指令分配。 正常存储器访问指令（例如，作为中断代码的一部分）可以执行并且将在高速缓存未命中的情况下从主存储器检索数据; 但是，这些指令不允许在缓存中分配条目。 只有预定的指令（例如，用于建立锁定的高速缓存条目的指令）可以在高速缓存中分配条目。 当锁定条目建立时，处理器退出BNCA模式，任何存储器访问指令都可以分配高速缓存条目。 可以通过在配置寄存器中设置位来指示BNCA模式。