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1.发明授权Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits 失效为制造集成电路提供可重复使用的可配置自检控制器的方法和系统
公开(公告)号：US6001662A
公开(公告)日：1999-12-14
申请号：US982440
申请日：1997-12-02
申请人： Anthony Correale, Jr. , James Norris Dieffenderfer , Trevor Scott Garner , Ronald William Kohake , Ketan Vitthal Patel
发明人： Anthony Correale, Jr. , James Norris Dieffenderfer , Trevor Scott Garner , Ronald William Kohake , Ketan Vitthal Patel
IPC分类号： G05B19/418 , H01L21/00
CPC分类号： G05B19/41875 , G05B2219/33323 , Y02P90/14 , Y02P90/16 , Y02P90/22
摘要： A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.
摘要翻译： 一种用于制造具有嵌入其中的多个存储器单元的集成电路器件的方法和系统。 最初，在集成电路装置内制造单个可重复使用的可配置测试电路。 然后识别嵌入集成电路设备内的每个存储单元的数量和类型。 最后，单个可重复使用的可配置测试电路被配置为响应于每个存储器单元的数量和类型的识别，使得仅需要一个测试电路用于具有嵌入其中的多个不同存储器单元的多个集成电路器件。 单个可重复使用的可配置测试电路可以放置在集成电路器件的固定磁芯内或外部。 此外，单个可重复使用的可配置测试电路可以包括阵列内置自检（ABIST）控制器，其包括分层存储器配置，其包括状态机，地址计数器，比较寄存器和数据模式发生器。
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公开(公告)号：US06192486B1
公开(公告)日：2001-02-20
申请号：US09133395
申请日：1998-08-13
IPC分类号： G06F1100
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to fuses and redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array. Although the present invention results in a reduction in the overall size of the array, and thus may result in performance degradation, it allows for the continued operation of the chip. For an embedded memory, the chip need not be discarded. Importantly, unlike the conventional method, the circuit in accordance with the present invention has the ability to handle defects which are introduced during usage, and defect detection and bypass are initiated each time the computer is initialized. Thus, the circuit in accordance with the present invention has utility subsequent to manufacturing testing. A chip with embedded memory which has the steering circuit of the present invention is thus more reliable than memory chips repaired with conventional methods.
摘要翻译： 本发明提供一种利用计算机芯片的存储器阵列绕过缺陷部分的方法和系统。 根据本发明的电路包括：寄存器，用于基于对存储器阵列中的至少一个缺陷部分的检测来控制存储器阵列的有效大小，以及多路复用器，用于接收存储器阵列的索引地址， 基于寄存器装置映射索引地址。 根据本发明的电路不使用保险丝进行维修，因此不需要芯片上用于这种保险丝的附加区域。 因此，它消除了与保险丝和冗余电池相关的制造过程中的复杂性。 根据本发明的电路动态地操纵阵列的地址以绕过阵列的缺陷区域。 尽管本发明导致阵列的总体尺寸的减小，并且因此可能导致性能下降，但是它允许芯片的继续操作。 对于嵌入式存储器，芯片不需要丢弃。 重要的是，与传统方法不同，根据本发明的电路具有处理使用期间引入的缺陷的能力，并且每当计算机初始化时启动缺陷检测和旁路。 因此，根据本发明的电路在制造测试之后具有实用性。 具有本发明的转向电路的具有嵌入式存储器的芯片因此比用常规方法修复的存储器芯片更可靠。
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公开(公告)号：US08739086B2
公开(公告)日：2014-05-27
申请号：US13364256
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译： 公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。 一些实施例基于集成电路的设计的行为表示创建物理设计表示。 行为表示可以包括具有一个或多个1×N构建块的RTL HDL。 这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。 另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中， 表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。
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公开(公告)号：US08122399B2
公开(公告)日：2012-02-21
申请号：US12200121
申请日：2008-08-28
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译： 公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。 一些实施例基于集成电路的设计的行为表示创建物理设计表示。 行为表示可以包括具有一个或多个1×N构建块的RTL HDL。 这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。 另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中， 表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。
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公开(公告)号：US07919819B2
公开(公告)日：2011-04-05
申请号：US12351015
申请日：2009-01-09
IPC分类号： H01L29/72
CPC分类号： H01L27/0207 , H01L27/11807
摘要： Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.
摘要翻译： 实施例包括经调整的多晶硅栅极间距与金属线间距关系，以改善面积标量，同时增加具有固定多晶硅栅极间距的ACLV容差。 在一些实施例中，调整用于至少一个金属化层的导线间距以匹配多晶硅栅极的间距。 在一个实施例中，与用于访问互连电池结构的输入或输出的用于与多晶硅栅极相同的取向运行的最低金属化层的下一个被放宽以匹配最小接触栅极间距，并且金属在每个多晶硅 门。 在另一个实施例中，多晶硅栅极间距可以被放宽以获得较小的最小公倍数，同时集成电路的导线间距可以减小最小偏移。
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6.发明授权公开(公告)号：US07908571B2
公开(公告)日：2011-03-15
申请号：US11971171
申请日：2008-01-08
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.
摘要翻译： 公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。 实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。 在一些实施例中，布线以防止短路。 在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。 在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。
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公开(公告)号：US07728362B2
公开(公告)日：2010-06-01
申请号：US11337010
申请日：2006-01-20
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译： 公开了使用门阵列来在集成电路内形成电容结构。 实施例包括在集成电路设计中具有P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列，将用于一个或多个P-fets和栅极的漏极和源耦合 将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。 在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。 在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。
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公开(公告)号：US06900662B2
公开(公告)日：2005-05-31
申请号：US10439362
申请日：2003-05-16
IPC分类号： H03K3/356 , H03K19/094
CPC分类号： H03K3/356113
摘要： A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator circuit includes a first transistor coupled to the transmitting voltage potential circuit and a clamping mechanism coupled to the first transistor. The circuit also includes a second transistor coupled to the first transistor, a higher voltage potential and the receiving voltage potential circuit. The circuit includes a third transistor coupled to the receiving voltage potential circuit, the higher voltage potential and the second transistor. Finally, the circuit includes a fourth transistor coupled to the receiving voltage potential circuit, and to a ground potential. The clamping mechanism clamps the input of the translator circuit such than an appropriate logic level is provided to the receiving voltage potential circuit and the leakage current is minimized when the transmitting voltage potential circuit is disabled. Accordingly, a level translator circuit is provided that operates effectively even when the transmitting voltage potential circuit is disabled. In addition, leakage current is minimized for the two distinct power supplies by clamping the input of the circuit such that an appropriate logical level is provided at the output of the circuit.
摘要翻译： 公开了一种在发射电压电位电路和接收电压电位电路之间使用的电平转换器电路。 转换器电路包括耦合到发射电压电位电路的第一晶体管和耦合到第一晶体管的钳位机构。 该电路还包括耦合到第一晶体管的第二晶体管，较高电压电位和接收电压电位电路。 该电路包括耦合到接收电压电位电路的第三晶体管，较高电压电位和第二晶体管。 最后，电路包括耦合到接收电压电位电路的第四晶体管和接地电位。 钳位机构夹持转换器电路的输入，这样，当接收电压电位电路提供适当的逻辑电平时，当禁止发射电压电位电路时，钳位电路的漏电流最小。 因此，提供了一种电平转换器电路，即使当禁止发射电压电位电路时也能有效地工作。 此外，通过钳位电路的输入使得在电路的输出处提供适当的逻辑电平，对于两个不同的电源，泄漏电流被最小化。
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公开(公告)号：US06593789B2
公开(公告)日：2003-07-15
申请号：US10020528
申请日：2001-12-14
IPC分类号： H03K3017
CPC分类号： H03K5/1565 , H03K2005/00039
摘要： A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle. For improved precision, a differential embodiment employs the same VCDCG.
摘要翻译： 精确可编程的占空比发生器，可以精确地产生用户定义的占空比时钟信号。 该电路包括许多通常已知的电路元件，例如数模转换器（DAC），低通滤波器（LPF）和运算跨导放大器（OTA），以及独特的电压控制占空比发生器（VCDCG） 。 该电路能够在宽范围的工作频率上产生精确的用户可编程占空比时钟信号。 VCDCG电路是独一无二的，采用多个阶段，每个阶段都有一个现有的饥饿逆变器，紧随其后的是常规逆变器，以允许占空比校正是加法或减法。 目前的饥饿逆变器由单一电压控制，这导致当前饥饿的逆变器的延迟仅在一个转换中降级/改善，以实现占空比的变化。 为了提高精度，差分实施例采用相同的VCDCG。
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公开(公告)号：US5534803A
公开(公告)日：1996-07-09
申请号：US420947
申请日：1995-04-12
IPC分类号： H03K5/01 , H03K19/003 , H03K19/0175 , H03B1/00
CPC分类号： H03K5/01 , H03K19/00384
摘要： A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.
摘要翻译： 用于补偿CMOS片外驱动器的小型高效控制电路和并入该控制电路的驱动电路。 控制电路使用异或门作为相位检测器来确定系统时钟与系统时钟的延迟版本之间的相位差。 RC滤波器使异或门的输出平滑，以产生与通过环境和过程变量在CMOS电路中引入的延迟成比例的电压。 来自RC滤波器的电压用作控制电压，以控制片外驱动电路的有效下拉器件的有效沟道宽度。 在CMOS集成电路芯片的I / O单元中使用使用控制电路的片外驱动器。
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