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    MEMORY CONTROLLER FOR MANAGING DATA AND ERROR INFORMATION
    91.
    发明申请
    MEMORY CONTROLLER FOR MANAGING DATA AND ERROR INFORMATION 有权

    公开(公告)号：US20230096375A1

    公开(公告)日：2023-03-30

    申请号：US17489336

    申请日：2021-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

    IPC: G06F3/06

    Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

    Memory management
    92.
    发明授权
    Memory management 有权

    公开(公告)号：US11550678B2

    公开(公告)日：2023-01-10

    申请号：US17206881

    申请日：2021-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

    IPC: G06F11/20 ,  G06F3/06

    Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

    CONTROLLER FOR MANAGING METRICS AND TELEMETRY
    94.
    发明申请
    CONTROLLER FOR MANAGING METRICS AND TELEMETRY 有权

    公开(公告)号：US20220326874A1

    公开(公告)日：2022-10-13

    申请号：US17687018

    申请日：2022-03-04

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Federica Cresci ,  Emanuele Confalonieri

    IPC: G06F3/06

    Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

    MEMORY MANAGEMENT
    97.
    发明申请
    MEMORY MANAGEMENT 有权

    公开(公告)号：US20210208988A1

    公开(公告)日：2021-07-08

    申请号：US17206881

    申请日：2021-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

    IPC: G06F11/20 ,  G06F3/06

    Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

    Data state synchronization
    98.
    发明授权
    Data state synchronization 有权

    公开(公告)号：US10943659B2

    公开(公告)日：2021-03-09

    申请号：US16744643

    申请日：2020-01-16

    Applicant: Micron Technology, Inc.

    Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

    IPC: G11C11/00 ,  G11C13/00 ,  G06F13/16

    Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

    DATA STATE SYNCHRONIZATION
    100.
    发明申请
    DATA STATE SYNCHRONIZATION 审中-公开

    公开(公告)号：US20200082900A1

    公开(公告)日：2020-03-12

    申请号：US16128113

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

    IPC: G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10

    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

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