公开(公告)号：US20140035640A1

公开(公告)日：2014-02-06

申请号：US14046796

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract translation: 公开了与改变用于执行命令的命令信号的定时相关的装置和方法。 一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加 。 时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。

公开(公告)号：US20140002148A1

公开(公告)日：2014-01-02

申请号：US13975100

申请日：2013-08-23

Applicant: Micron Technology, Inc.

Inventor： Eric Booth ,  Tyler J. Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

IPC: H03L1/00

CPC classification number: H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用