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1.发明申请HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION 有权高速，宽频范围，数字相位混频器及操作方法公开(公告)号：US20130241608A1
公开(公告)日：2013-09-19
申请号：US13889099
申请日：2013-05-07
Applicant: Micron Technology, Inc.
Inventor： Chang-ki Kwon , Eric Booth
CPC classification number: H03L7/00 , G06G7/12 , H03K17/00 , H03L7/0814
Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.
Abstract translation: 本公开涉及与输入缓冲器组合的单位相混合器。 单相混合器具有用于将输出端拉至第一电压的上拉路径。 所述上拉路径具有响应于第一使能信号的第一晶体管和响应于第一时钟信号的串联连接的第二晶体管。 单相混合器具有用于将输出端子向下拉到第二电压的下拉路径。 所述下拉路径具有响应于第二时钟信号的第三晶体管和响应于第二使能信号的串联连接的第四晶体管。 输入缓冲器使第一和第二时钟信号偏移不同的量，以使得能够进行先前的断开操作方法，使得第一电压不连接到第二电压。 单相混频器可以用作更复杂的混频器中的构建块，其可以包括对输入时钟加权的能力以及为某些信号提供前馈路径。 由于抽象的规则，本摘要不应用于解释索赔。
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Patent Agency Ranking
公开(公告)号：US08989692B2
公开(公告)日：2015-03-24
申请号：US13889099
申请日：2013-05-07
Applicant: Micron Technology, Inc.
Inventor： Chang-ki Kwon , Eric Booth
CPC classification number: H03L7/00 , G06G7/12 , H03K17/00 , H03L7/0814
Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.
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公开(公告)号：US20140218077A1
公开(公告)日：2014-08-07
申请号：US14246328
申请日：2014-04-07
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC: H03K5/13
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
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公开(公告)号：US08692603B2
公开(公告)日：2014-04-08
申请号：US13975100
申请日：2013-08-23
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC: H03K3/00
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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公开(公告)号：US20140002148A1
公开(公告)日：2014-01-02
申请号：US13975100
申请日：2013-08-23
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC: H03L1/00
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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公开(公告)号：US08963604B2
公开(公告)日：2015-02-24
申请号：US14246328
申请日：2014-04-07
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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