公开(公告)号：US20220277987A1

公开(公告)日：2022-09-01

申请号：US17749282

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20220223602A1

公开(公告)日：2022-07-14

申请号：US17705680

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US11367726B2

公开(公告)日：2022-06-21

申请号：US17079612

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  G11C11/402

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US11342218B1

公开(公告)日：2022-05-24

申请号：US17086536

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L27/11 ,  H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20220139767A1

公开(公告)日：2022-05-05

申请号：US17086536

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US11309315B2

公开(公告)日：2022-04-19

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US20220077150A1

公开(公告)日：2022-03-10

申请号：US17016724

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Yuichi Yokoyama ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

公开(公告)号：US20220037334A1

公开(公告)日：2022-02-03

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US11239117B1

公开(公告)日：2022-02-01

申请号：US17004084

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Scott E. Sills

IPC: H01L21/8234 ,  H01L21/822 ,  H01L29/66 ,  H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L21/02 ,  H01L27/06

Abstract: Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.

公开(公告)号：US11227864B1

公开(公告)日：2022-01-18

申请号：US16986610

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Scott E. Sills

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: Systems, methods and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes forming elongated vertical, pillar columns with sidewalls in a vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical openings. Portions of the first conductive material are removed to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns. A second vertical opening is formed through the vertical stack to expose a first region of the sacrificial material. A third vertical opening is formed through the vertical stack to in which to form a storage node electrically coupled to the first source/drain material.