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    Array Of Capacitors And Method Used In Forming An Array Of Capacitors
    1.
    发明申请
    Array Of Capacitors And Method Used In Forming An Array Of Capacitors 有权

    公开(公告)号：US20220208771A1

    公开(公告)日：2022-06-30

    申请号：US17696160

    申请日：2022-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H01L27/108 ,  H01L27/01

    Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

    MICROELECTRONIC DEVICE WITH THICK CONDUCTIVE STAIRCASED STEPS FOR 3D DRAM, AND RELATED SYSTEMS AND METHODS OF FORMATION
    2.
    发明申请
    MICROELECTRONIC DEVICE WITH THICK CONDUCTIVE STAIRCASED STEPS FOR 3D DRAM, AND RELATED SYSTEMS AND METHODS OF FORMATION 有权

    公开(公告)号：US20250112151A1

    公开(公告)日：2025-04-03

    申请号：US18781810

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Scott E. Sills ,  Yuichi Yokoyama

    IPC: H01L23/528 ,  H01L23/532 ,  H10B12/00

    Abstract: A microelectronic device includes a stack structure with tiers individually extending through an array area and into a staircase area horizontally neighboring the array area. The array area includes at least one access device. The staircase area includes a staircase structure having steps at ends of the tiers. At least some of the tiers individually include a conductive region, insulative regions, and discrete regions of semiconductor material. The conductive region includes conductive material extending through the array area and into the staircase area. The insulative regions are in both the array area and the staircase area. The discrete regions of semiconductor material are in the array area. The staircase area is substantially free of the semiconductor material. The conductive material is thicker in the staircase area than in the array area. Related electronic systems and methods of formation are also disclosed.

    Widened conductive line structures and staircase structures for semiconductor devices
    4.
    发明授权
    Widened conductive line structures and staircase structures for semiconductor devices 有权

    公开(公告)号：US11950403B2

    公开(公告)日：2024-04-02

    申请号：US17078201

    申请日：2020-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/30 ,  H01L23/5226 ,  H10B12/01

    Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

    Support pillars for vertical three-dimensional (3D) memory
    5.
    发明授权
    Support pillars for vertical three-dimensional (3D) memory 有权

    公开(公告)号：US11476254B2

    公开(公告)日：2022-10-18

    申请号：US17162525

    申请日：2021-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H01L27/108 ,  H01L27/24

    Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers. A third vertical opening is formed through the vertical stack extending to expose second sidewalls adjacent areas where horizontal access devices will be formed. The sacrificial material is selectively etched to form first horizontal openings, removing the sacrificial material a first horizontal distance (D1) back from the third vertical opening. A fourth vertical opening is formed through the vertical stack to expose third sidewalls adjacent areas where storage nodes will be formed. The support-pillar material of the formed structural support pillars may serve as an etch stop in selectively etching to form the second horizontal openings.

    WIDENED CONDUCTIVE LINE STRUCTURES AND STAIRCASE STRUCTURES FOR SEMICONDUCTOR DEVICES
    6.
    发明申请
    WIDENED CONDUCTIVE LINE STRUCTURES AND STAIRCASE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220130830A1

    公开(公告)日：2022-04-28

    申请号：US17078201

    申请日：2020-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H01L27/108 ,  H01L23/522

    Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

    Integrated memory and integrated assemblies
    7.
    发明授权
    Integrated memory and integrated assemblies 有权

    公开(公告)号：US10312241B1

    公开(公告)日：2019-06-04

    申请号：US15965717

    申请日：2018-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H01L27/108 ,  H01L27/06 ,  H01L27/02 ,  H01L49/02

    Abstract: Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).

    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS
    8.
    发明公开
    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 审中-公开

    公开(公告)号：US20240164083A1

    公开(公告)日：2024-05-16

    申请号：US18054291

    申请日：2022-11-10

    Applicant: Micron Technology, Inc.

    Inventor： Yuichi Yokoyama

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/1085

    Abstract: A microelectronic device comprises a stack structure comprising an array region comprising first conductive structures vertically spaced from one another, and a staircase region horizontally neighboring the array region and comprising second conductive structures vertically spaced from one another and coupled to the first conductive structures. The second conductive structures individually comprise portions extending in a first horizontal direction, and additional portions extending in a second horizontal direction transverse to the first horizontal direction. The staircase region comprises staircase structures having steps partially defined by edges of the second conductive structures. Some of the steps extend in the first horizontal direction and some others of the steps extend in the second horizontal direction. Related memory devices, electronic systems, and methods are also described.

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