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1.发明公开公开(公告)号：US20240038588A1
公开(公告)日：2024-02-01
申请号：US17815359
申请日：2022-07-27
Applicant: Micron Technology, Inc.
Inventor： Terrence B. McDaniel , Vinay Nair , Russell A. Benson , Christopher W. Petz , Si-Woo Lee , Silvia Borsari , Ping Chieh Chiang , Luca Fumagalli
IPC: H01L21/768 , H01L27/108
CPC classification number: H01L21/76897 , H01L27/10855 , H01L27/10885
Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.
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公开(公告)号：US20230345708A1
公开(公告)日：2023-10-26
申请号：US17729450
申请日：2022-04-26
Applicant: Micron Technology, Inc.
Inventor： Kuo-Chen Wang , Terrence B. McDaniel , Russell A. Benson , Vinay Nair
IPC: H01L27/108
CPC classification number: H01L27/10885 , H01L27/10888 , H01L27/10897
Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.
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公开(公告)号：US20230005932A1
公开(公告)日：2023-01-05
申请号：US17364281
申请日：2021-06-30
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Kunal R. Parekh , Terrence B. McDaniel , Beau D. Barry
IPC: H01L27/108
Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.
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公开(公告)号：US20240379596A1
公开(公告)日：2024-11-14
申请号：US18660210
申请日：2024-05-09
Applicant: Micron Technology, Inc.
Inventor： Bharat Bhushan , Terrence B. McDaniel , Kunal R. Parekh , Bret K. Street , Akshay N. Singh
IPC: H01L23/00 , H01L21/311 , H01L23/48 , H01L25/065
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.
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公开(公告)号：US20240071989A1
公开(公告)日：2024-02-29
申请号：US18237202
申请日：2023-08-23
Applicant: Micron Technology, Inc.
Inventor： Kyle K. Kirby , Terrence B. McDaniel
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80125 , H01L2224/80895 , H01L2224/80896
Abstract: This document discloses techniques, apparatuses, and systems for semiconductor device circuitry formed from remote reservoirs. A semiconductor assembly includes a first semiconductor die with a layer of dielectric material having an opening. The first semiconductor die further includes a reservoir of conductive material having a first portion located adjacent to the opening, a second portion remote from the opening, and a third portion coupling the first portion and the second portion. A second semiconductor die includes a layer of dielectric material and a contact pad corresponding to the opening. The reservoir of conductive material is heated to volumetrically expand the second portion into the third portion, the third portion into the first portion, and the first portion through the opening to form an interconnect electrically coupling the first semiconductor die and the second semiconductor die at the contact pad. In this way, a connected semiconductor device may be assembled.
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公开(公告)号：US20240071823A1
公开(公告)日：2024-02-29
申请号：US18237174
申请日：2023-08-23
Applicant: Micron Technology, Inc.
Inventor： Kyle K. Kirby , Terrence B. McDaniel
IPC: H01L21/768 , H01L23/00 , H01L23/48 , H01L23/522 , H01L23/532
CPC classification number: H01L21/76882 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/53228 , H01L24/08 , H01L2224/08145
Abstract: A semiconductor assembly is described that includes a semiconductor die having first circuitry. The semiconductor die further includes second circuitry with a reservoir of conductive material and an interlayer dielectric having one or more openings between the first circuitry and the reservoir of conductive material. The reservoir of conductive material is heated effective to cause the reservoir of conductive material to volumetrically expand through the one or more openings to create one or more vias that electrically couples the first circuitry and the reservoir of conductive material. In doing so, a connected semiconductor device may be assembled.
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7.发明申请
公开(公告)号：US20230014320A1
公开(公告)日：2023-01-19
申请号：US17947401
申请日：2022-09-19
Applicant: Micron Technology, Inc.
Inventor： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.
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8.发明授权
公开(公告)号：US11488981B2
公开(公告)日：2022-11-01
申请号：US16934607
申请日：2020-07-21
Applicant: Micron Technology, Inc.
Inventor： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.
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公开(公告)号：US20220059469A1
公开(公告)日：2022-02-24
申请号：US16999817
申请日：2020-08-21
Applicant: Micron Technology, Inc.
Inventor： Russell A. Benson , Davide Colombo , Yan Li , Terrence B. McDaniel , Vinay Nair , Silvia Borsari
IPC: H01L23/552 , H01L27/108
Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
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10.发明申请
公开(公告)号：US20220028903A1
公开(公告)日：2022-01-27
申请号：US16934607
申请日：2020-07-21
Applicant: Micron Technology, Inc.
Inventor： Yi Fang Lee , Jaydip Guha , Lars P. Heineck , Kamal M. Karda , Si-Woo Lee , Terrence B. McDaniel , Scott E. Sills , Kevin J. Torek , Sheng-Wei Yang
Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.
