公开(公告)号：US12224201B2

公开(公告)日：2025-02-11

申请号：US18403866

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/02 ,  H01L21/762 ,  H01L25/00 ,  H01L25/18

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20240292607A1

公开(公告)日：2024-08-29

申请号：US18583319

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Jun Ho Lee ,  Byung Yoon Kim ,  Sangmin Hwang

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02

Abstract: A variety of applications can include an apparatus having a device including line contacts to closely-spaced conductive signal lines structured such that a sufficient margin for shorts between a signal line and a line contact to a directly adjacent signal line is maintained even with a misalignment of the line contact. In an embodiment, formation of a memory device can include forming a line contact on and contacting an access line for an array of memory cells, using a two stage removal procedure of different removal processes. The two stage removal procedure can include removing a portion of processing layers above an insulating protective layer positioned on the access line and selectively removing the insulating protective layer, exposing a portion of the access line, without removing material of the access line. The line contact can be formed on and contacting the top exposed portion of the access line.

公开(公告)号：US20240153813A1

公开(公告)日：2024-05-09

申请号：US18403866

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L21/76251 ,  H01L21/02532 ,  H01L21/02598 ,  H01L25/18 ,  H01L25/50 ,  H01L21/02381

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20220285365A1

公开(公告)日：2022-09-08

申请号：US17189485

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US20240260251A1

公开(公告)日：2024-08-01

申请号：US18419808

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Dong Wan Kim ,  Russell A. Benson ,  Byung Yoon Kim

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. The conductive gate comprises part of one of a plurality of conductive-gate lines in a substrate. Lines of conductive material are formed directly above and directly against individual of the one and another source/drain regions. Individual of the lines of the conductive material are between immediately-laterally-adjacent of the conductive-gate lines. The lines of the conductive material directly above the another source/drain regions are etched through to form islands of the conductive material that are individually directly above and directly against the individual one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions through individual of the islands of the conductive material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240079474A1

公开(公告)日：2024-03-07

申请号：US17903414

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H01L29/66 ,  H01L29/739

CPC classification number: H01L29/66348 ,  H01L29/7395

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include transistors formed from a plurality of semiconductor fins, and using a number of conductive lines passing through trenches between the fins to serve as a gate for the transistor.

公开(公告)号：US11152375B2

公开(公告)日：2021-10-19

申请号：US16259330

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim

IPC: H01L27/108 ,  H01G4/008 ,  H01G4/08 ,  H01G4/012 ,  H01L21/02

Abstract: Methods, apparatuses, and systems related to patterning a material over a sense line contact are described. An example method includes forming a sense line contact pattern at an angle to a sense line direction over semiconductor structures on a substrate, wherein the angle to the sense line direction is formed along a path between a sense line contact in a first sense line column and a sense line contact in a second sense line column. The example method further includes removing a portion of a mask material corresponding to the sense line contact pattern to form sense line contacts.

公开(公告)号：US20200243540A1

公开(公告)日：2020-07-30

申请号：US16259330

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim

IPC: H01L27/108 ,  H01L21/02 ,  H01G4/08 ,  H01G4/012 ,  H01G4/008

Abstract: Methods, apparatuses, and systems related to patterning a material over a sense line contact are described. An example method includes forming a sense line contact pattern at an angle to a sense line direction over semiconductor structures on a substrate, wherein the angle to the sense line direction is formed along a path between a sense line contact in a first sense line column and a sense line contact in a second sense line column. The example method further includes removing a portion of a mask material corresponding to the sense line contact pattern to form sense line contacts.

公开(公告)号：US11869803B2

公开(公告)日：2024-01-09

申请号：US17749282

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/76251 ,  H01L21/02532 ,  H01L21/02598 ,  H01L25/18 ,  H01L25/50 ,  H01L21/02381

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20230240067A1

公开(公告)日：2023-07-27

申请号：US18131097

申请日：2023-04-05

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/50 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/02603 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/09 ,  H10B12/30

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.