公开(公告)号：US20070236276A1

公开(公告)日：2007-10-11

申请号：US11764605

申请日：2007-06-18

申请人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： H01L29/94

CPC分类号： G05F3/205

摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用 基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

公开(公告)号：US07236035B2

公开(公告)日：2007-06-26

申请号：US10990537

申请日：2004-11-18

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

摘要翻译： 第一个逻辑电路的电源电压被控制。 第二逻辑电路响应于外部时钟信号而工作。 调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。 调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

公开(公告)号：US20060267020A1

公开(公告)日：2006-11-30

申请号：US11490107

申请日：2006-07-21

申请人： Hiroyuki Hara ,  Satoshi Inoue

发明人： Hiroyuki Hara ,  Satoshi Inoue

IPC分类号： H01L29/04

CPC分类号： H01L27/1281 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/78675

摘要： The invention provides a method of manufacturing a semiconductor device, capable of enhancing characteristics of each semiconductor element constituting the semiconductor device, while reducing or suppressing non-uniformity in the characteristics thereof. When forming a thin-film circuit constructed by arranging a plurality of pixel circuits on a glass substrate, first, a plurality of concave portions to be seeds in crystallizing a semiconductor film are formed on the glass substrate with a pitch n times an array pitch of a plurality of pixel circuits. Then, an amorphous silicon film is formed on the glass substrate on which the concave portions are formed, and by crystallizing the silicon film by heating, a substantially monocrystalline silicon film is formed within a region centered on the concave portions. Using each of the substantially monocrystalline silicon film formed substantially centered around the respective concave portions, pixel circuits are formed.

摘要翻译： 本发明提供了一种制造半导体器件的方法，该半导体器件能够在减少或抑制其特性不均匀性的同时，提高构成半导体器件的每个半导体元件的特性。 当形成通过在玻璃基板上排列多个像素电路而构成的薄膜电路时，首先，在玻璃基板上形成半晶体半导体晶体化的多个凹入部分，其间距为n倍的阵列间距 多个像素电路。 然后，在形成有凹部的玻璃基板上形成非晶硅膜，通过加热使硅膜结晶化，在以凹部为中心的区域内形成大致单晶硅膜。 使用基本上围绕各个凹部中心地形成的基本单晶硅膜中的每一个，形成像素电路。

公开(公告)号：US07126349B2

公开(公告)日：2006-10-24

申请号：US10911674

申请日：2004-08-05

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G01R27/26

CPC分类号： G06K9/0002

摘要： Aspects of the invention can provide a fingerprint sensor with high sensing precision. The fingerprint sensor according to the invention can include capacitance detection circuits that output detection signals, which each correspond to a capacitance formed between a subject surface and the fingerprint sensor, to signal transmitting paths, and an amplification circuit that amplifies the detection signals outputted to the signal transmitting paths. The individual signal transmitting paths can be respectively connected to at least two capacitance detection circuits and the fingerprint sensor further includes a resetting means that resets the potential of the signal transmitting paths before the detection signals are outputted from the capacitance detection circuits to the signal transmitting paths.

摘要翻译： 本发明的方面可以提供具有高感测精度的指纹传感器。 根据本发明的指纹传感器可以包括电容检测电路，其输出检测信号，每个检测信号各自对应于在被摄体表面和指纹传感器之间形成的电容，用于信号传送路径;以及放大电路，放大输出到 信号传输路径。 各个信号传输路径可以分别连接到至少两个电容检测电路，并且指纹传感器还包括复位装置，其在检测信号从电容检测电路输出到信号传输路径之前复位信号传输路径的电位 。

公开(公告)号：US07116116B2

公开(公告)日：2006-10-03

申请号：US10958483

申请日：2004-10-06

申请人： Hiroaki Ebihara ,  Mitsutoshi Miyasaka ,  Hiroyuki Hara

发明人： Hiroaki Ebihara ,  Mitsutoshi Miyasaka ,  Hiroyuki Hara

IPC分类号： G01R27/26

CPC分类号： G01D5/2405 ,  G01D5/24 ,  G07C9/00087 ,  G07C2009/00095

摘要： To provide a superior capacitance detecting device, a capacitance detecting device includes M row lines and N column lines that are arranged in a matrix, capacitance detecting elements provided at intersections therebetween, and power lines. The capacitance detecting element includes a signal detecting element and a signal amplifying element. The signal detecting element includes a capacitance detecting electrode, a capacitance detecting dielectric film, and a reference capacitor. The signal amplifying element is composed of a thin film semiconductor device having a gate electrode, a gate insulating film, and a semiconductor film, and an electrode of the reference capacitor is connected to the row line.

摘要翻译： 为了提供优异的电容检测装置，电容检测装置包括矩阵排列的M行和N列线，设置在它们之间的交叉处的电容检测元件和电力线。 电容检测元件包括信号检测元件和信号放大元件。 信号检测元件包括电容检测电极，电容检测电介质膜和参考电容器。 信号放大元件由具有栅电极，栅极绝缘膜和半导体膜的薄膜半导体器件构成，参考电容器的电极与行线连接。

公开(公告)号：US20060208974A1

公开(公告)日：2006-09-21

申请号：US11354129

申请日：2006-02-15

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G09G3/30

CPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2310/061 ,  G09G2360/16

摘要： An organic electroluminescent device, comprises a plurality of pixels each including a light-emitting element, and a drive device adjusting a light-emission period of the light-emitting element included in each of the pixels in accordance with a luminance ratio of an image to be displayed.

摘要翻译： 一种有机电致发光器件，包括每个包括发光元件的多个像素，以及驱动装置，其根据图像的亮度比调整包括在每个像素中的发光元件的发光周期 被显示。

公开(公告)号：US20060208656A1

公开(公告)日：2006-09-21

申请号：US11354031

申请日：2006-02-15

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G09G3/10

CPC分类号： G09G3/3233 ,  G09G3/2014 ,  G09G3/2022 ,  G09G3/3266 ,  G09G3/3291 ,  G09G5/363 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/043 ,  G09G2320/0666

摘要： An organic electroluminescent device including: a plurality of pixels, each having a red light emitting element to emit red light, a green light emitting element to emit green light, and a blue light emitting element to emit blue light; and a drive device adjusting a luminance ratio among the red light, the green light, and the blue light by adjusting light emitting time of each of the red light emitting element, the green light emitting element, and the blue light emitting element.

摘要翻译： 一种有机电致发光器件，包括：多个像素，每个具有发射红光的红色发光元件，发出绿色光的绿色发光元件和发出蓝色光的蓝色发光元件; 以及驱动装置，通过调节红色发光元件，绿色发光元件和蓝色发光元件中的每一个的发光时间来调节红色光，绿色光和蓝色光之间的亮度比。

公开(公告)号：US20060198198A1

公开(公告)日：2006-09-07

申请号：US11342617

申请日：2006-01-31

申请人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

发明人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C5/147

摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

摘要翻译： 根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

公开(公告)号：US20060165546A1

公开(公告)日：2006-07-27

申请号：US11337079

申请日：2006-01-23

申请人： Shigeki Yamada ,  Hiroyuki Hara

发明人： Shigeki Yamada ,  Hiroyuki Hara

IPC分类号： B22F7/02

CPC分类号： B22F3/1055 ,  B22F2003/1056 ,  B33Y10/00 ,  B33Y30/00 ,  Y02P10/295

摘要： The present invention teaches a method and an apparatus for manufacturing a three-dimensional object having a smooth outer surface, without any step of removing a surface layer each time a sintered layer is formed so as to manufacture a three-dimensional object consisting of integrally built-up sintered layers. The method may include the steps of: (i) supplying powder particles (10) onto a moving area while heating the powder particles (10) with heat (20) from a high-density energy heat source so as to form a sintered layer (16); and (ii) supplying powder particles 10 onto a moving area on the sintered layer while heating the powder particles (10) with heat (20) from the high-density energy heat source so as to form another sintered layer (18) integrally on the sintered layer (16), wherein the step (ii) is repeated a predetermined number of times.

摘要翻译： 本发明教导了一种用于制造具有光滑外表面的三维物体的方法和装置，每次形成烧结层时，没有任何步骤去除表面层，以便制造由整体构成的三维物体 - 烧结层。 该方法可以包括以下步骤：（i）将粉末颗粒（10）供应到移动区域上，同时用高密度能量热源从粉末颗粒（20）加热粉末颗粒（20）以形成烧结层（ 16）; 和（ii）将粉末颗粒10供应到烧结层上的移动区域上，同时用高密度能量热源用热量（20）加热粉末颗粒（10），以便形成另一个烧结层（18） 烧结层（16），其中步骤（ii）重复预定次数。

公开(公告)号：US07081765B2

公开(公告)日：2006-07-25

申请号：US10925031

申请日：2004-08-25

申请人： Mitsutoshi Miyasaka ,  Hiroyuki Hara

发明人： Mitsutoshi Miyasaka ,  Hiroyuki Hara

IPC分类号： G01R27/26

CPC分类号： G06K9/0002

摘要： Aspects of the invention provide a superior electrostatic capacitance detecting device. The electrostatic capacitance detection device can include M number of row lines, N number of column lines, and electrostatic capacitance detecting devices formed at intersections of these lines. The electrostatic capacitance detecting element can include a signal detection element, a signal amplifying element, a column selecting element, and a row selecting element, and the signal detection element can include a capacitance detecting electrode, a capacitance detecting dielectric layer, and a reference capacitor, and one electrode of the reference capacitor connects to a column line.

摘要翻译： 本发明提供一种优良的静电电容检测装置。 静电电容检测装置可以包括M行行线，N列列线和在这些线的交点处形成的静电电容检测装置。 静电电容检测元件可以包括信号检测元件，信号放大元件，列选择元件和行选择元件，并且信号检测元件可以包括电容检测电极，电容检测电介质层和参考电容器 ，参考电容器的一个电极连接到列线。