公开(公告)号：US20060198198A1

公开(公告)日：2006-09-07

申请号：US11342617

申请日：2006-01-31

申请人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

发明人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C5/147

摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

摘要翻译： 根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

公开(公告)号：US07417489B2

公开(公告)日：2008-08-26

申请号：US11342617

申请日：2006-01-31

申请人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

发明人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

IPC分类号： G05F1/10

CPC分类号： G11C5/147

摘要： A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

摘要翻译： 一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

公开(公告)号：US07236035B2

公开(公告)日：2007-06-26

申请号：US10990537

申请日：2004-11-18

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

摘要翻译： 第一个逻辑电路的电源电压被控制。 第二逻辑电路响应于外部时钟信号而工作。 调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。 调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

公开(公告)号：US20060061401A1

公开(公告)日：2006-03-23

申请号：US10990537

申请日：2004-11-18

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

摘要翻译： 第一个逻辑电路的电源电压被控制。 第二逻辑电路响应于外部时钟信号而工作。 调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。 调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

公开(公告)号：US07551019B2

公开(公告)日：2009-06-23

申请号：US11764605

申请日：2007-06-18

申请人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G05F3/16 ,  H03L1/00

CPC分类号： G05F3/205

摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用 基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

公开(公告)号：US20050093611A1

公开(公告)日：2005-05-05

申请号：US10899004

申请日：2004-07-27

申请人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K3/01 ,  H03K17/00

CPC分类号： G05F3/205

摘要： A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置产生电路，其基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差将单独的所述阱区域施加衬底偏置，以使各MOS晶体管的阈值电压与正常阈值电压一致。

公开(公告)号：US20070236276A1

公开(公告)日：2007-10-11

申请号：US11764605

申请日：2007-06-18

申请人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： H01L29/94

CPC分类号： G05F3/205

摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用 基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

公开(公告)号：US20070285152A1

公开(公告)日：2007-12-13

申请号：US11758343

申请日：2007-06-05

申请人： Tetsuya FUJITA ,  Mototsugu Hamada

发明人： Tetsuya FUJITA ,  Mototsugu Hamada

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： A power supply voltage controlling circuit that controls an output voltage at an output terminal to a desired set voltage, has a voltage regulator circuit that is connected to a first power supply and a second power supply that outputs a higher voltage than said first power supply, supplies a current to said output terminal from at least any of said first power supply and said second power supply, and compares the output voltage at said output terminal with a first reference voltage to adjust said output voltage to approach said first reference voltage; and a controller circuit that supplies said first reference voltage to said voltage regulator circuit and controls said voltage regulator circuit by outputting, to said voltage regulator circuit, at least any of a first enable signal for enabling said first power supply to supply a current to said output terminal and a second enable signal for enabling said second power supply to supply a current to said output terminal.

摘要翻译： 将输出端子处的输出电压控制为期望设定电压的电源电压控制电路具有连接到第一电源的电压调节器电路和输出比所述第一电源高的电压的第二电源， 从所述第一电源和所述第二电源中的至少一个向所述输出端提供电流，并将所述输出端的输出电压与第一参考电压进行比较，以调整所述输出电压以接近所述第一参考电压; 以及控制器电路，其将所述第一参考电压提供给所述电压调节器电路，并且通过向所述稳压器电路输出至少任一第一使能信号来控制所述电压调节器电路，以使所述第一电源能够向所述电压调节器电路提供电流 输出端子和第二使能信号，用于使所述第二电源能够向所述输出端子提供电流。

公开(公告)号：US07586364B2

公开(公告)日：2009-09-08

申请号：US11758343

申请日：2007-06-05

申请人： Tetsuya Fujita ,  Mototsugu Hamada

发明人： Tetsuya Fujita ,  Mototsugu Hamada

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.

摘要翻译： 电源电压控制电路具有电压调节器电路，其从第一电源和第二电源中的至少任一个向输出端提供电流，并且将输出端子处的输出电压与第一参考电压进行比较以进行调整 输出电压接近第一参考电压; 以及控制器电路，其将所述第一参考电压提供给所述电压调节器电路，并且通过向所述稳压器电路输出至少任一第一使能信号来控制所述稳压器电路，以使所述第一电源能够向所述电压调节器电路提供电流 输出端子和第二使能信号，用于使第二电源能够向输出端子提供电流。

公开(公告)号：US07397271B2

公开(公告)日：2008-07-08

申请号：US11502572

申请日：2006-08-11

申请人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

发明人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.

摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行 基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管 基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流 的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。