公开(公告)号：US06658556B1

公开(公告)日：2003-12-02

申请号：US09364288

申请日：1999-07-30

Applicant: Ravi Kumar Arimilli ,  Leo James Clark ,  John Steve Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steve Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

IPC: G06F1730

CPC classification number: G06F9/3885 ,  G06F9/3013 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/384 ,  G06F9/3891

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.

Abstract translation: 处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。 执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。 加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。

公开(公告)号：US06629214B1

公开(公告)日：2003-09-30

申请号：US09437186

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F1300

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.

Abstract translation: 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 额外的缓存状态允许优化缓存状态转换序列。 特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器 一个修改。 通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

公开(公告)号：US06622222B2

公开(公告)日：2003-09-16

申请号：US09843071

申请日：2001-04-26

Applicant: Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Warren Edward Maule

Inventor： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Warren Edward Maule

IPC: G06F1300

CPC classification number: G06F13/161

Abstract: Disclosed is a method and memory subsystem that allows for speculative issuance of reads to a DRAM array to provide efficient utilization of the data out bus and faster read response for accesses to a single DRAM array. Two read requests are issued simultaneously to a first and second DRAM in the memory subsystem, respectively. Data issued from the first DRAM is immediately placed on the data out bus, while data issued from the second DRAM is held in an associated buffer. The processor or memory controller then generates a release signal if the second read is not speculative or is correctly speculated. The release signal is sent to the second DRAM after the first issued data is placed on the bus. The release signal releases the data held in the buffer associated with the second DRAM from the buffer to the data out bus. Because the data has already been issued when the release signal is received, no loss of time is incurred in issuing the data from the DRAM and only a small clock cycle delay occurs between the first issued data and the second issued data on the data out bus.

Abstract translation: 公开了一种方法和存储器子系统，其允许对DRAM阵列的读取的推测性发布以提供数据输出总线的有效利用和对单个DRAM阵列的访问的更快的读取响应。 两个读取请求分别同时发送到存储器子系统中的第一和第二DRAM。 从第一DRAM发出的数据立即被放置在数据输出总线上，而从第二DRAM发出的数据保持在相关的缓冲器中。 如果第二次读取不是推测性的或者被正确推测，则处理器或存储器控制器然后产生释放信号。 在第一个发布的数据放在总线上之后，释放信号被发送到第二个DRAM。 释放信号将保存在与第二DRAM相关联的缓冲器中的数据从缓冲器释放到数据输出总线。 由于在接收到释放信号时已经发出数据，所以在从DRAM发出数据时不会发生时间损失，并且在数据总线上的第一次发布的数据和第二个发出的数据之间只发生小的时钟周期延迟 。

公开(公告)号：US06591321B1

公开(公告)日：2003-07-08

申请号：US09437200

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F12/0831

Abstract: A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system. All of the bus accessible memory devices on the cache bus line send snoop responses in response to the bus master signal based on the designated snoop response group. The snoop responses are sent to the combined response logic system. A combined response by the combined response logic system is determined based on the appropriate combined response encoding logic determined by the designated and latched snoop response group. The combined response is sent to all of the bus accessible memory devices on the cache bus line.

Abstract translation: 一种用于处理和处理处理器请求的多处理器系统总线协议系统和方法，所述多处理器系统具有被窥探的多个总线可访问存储器件。 至少有一条总线。 提供了来自总线可访问存储器设备的不同类型的窥探响应的侦听响应组。 在每个窥探响应组中提供不同的传输类型。 指定提供总线主机信号的总线主设备。 总线主设备接收处理器请求。 根据处理器请求适当地指定其中一个侦听响应组和传输类型之一。 总线主机信号由侦听响应组，传输类型，有效请求信号和高速缓存线地址来制定。 总线主机信号被发送到高速缓存总线上的所有总线可访问存储器件和组合响应逻辑系统。 基于指定的窥探响应组，高速缓存总线上的所有总线可访问存储器件响应于总线主机信号发送窥探响应。 侦听响应被发送到组合的响应逻辑系统。 基于由指定和锁存的窥探响应组确定的适当的组合响应编码逻辑来确定组合响应逻辑系统的组合响应。 组合的响应被发送到高速缓存总线上的所有总线可访问存储器件。

公开(公告)号：US06581116B1

公开(公告)日：2003-06-17

申请号：US09437042

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Warren Edward Maule

Inventor： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Warren Edward Maule

IPC: G06F1300

CPC classification number: G06F13/4269

Abstract: A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus master consecutively issues multiple packets, such as command packets, to the bus slave on the bus. The packets include order sensitive packets and non-order sensitive packets. In response to a temporary inability of the bus slave to process a particular one of the order sensitive packets due to a lack of resources, the bus slave keeps retrying the particular order sensitive packet. When resources become available, the bus slave processes the retried order sensitive packets in order while allowing the retried non-order sensitive packets to be processed in any order.

Abstract translation: 公开了一种用于在数据处理系统内的总线上发送有序分组的方法。 数据处理系统包括连接在总线主机和总线从机之间的总线。 总线主机在总线上连续向总线从站发出多个数据包，如命令数据包。 数据包包括顺序敏感数据包和非顺序敏感数据包。 由于总线从属单元由于缺乏资源而暂时无法处理特定的一个敏感数据包，所以总线从站不断重试特定的顺序敏感数据包。 当资源变得可用时，总线从站按顺序处理重试顺序敏感数据包，同时允许以任何顺序处理重试的非顺序敏感数据包。

公开(公告)号：US06553462B2

公开(公告)日：2003-04-22

申请号：US09753057

申请日：2000-12-28

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie

IPC: G06F1200

CPC classification number: G06F12/0831

Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.

公开(公告)号：US06519665B1

公开(公告)日：2003-02-11

申请号：US09436900

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC: G06F1516

CPC classification number: G06F15/16

Abstract: A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.

Abstract translation: 数据处理系统至少包括第一和第二节点以及具有耦合的第一和第二段的分段互连。 第一节点包括第一段和耦合到第一段的第一和第二代理，并且第二节点包括第二段和耦合到第二段的第三代理。 第一节点还包括消除逻辑，响应于第一代理在从第一段传播到第二段的分段互连上发出请求，并且第二代理指示服务该请求的能力，向第三代发送取消消息 代理指示第三代理人忽略该请求。

公开(公告)号：US06507880B1

公开(公告)日：2003-01-14

申请号：US09435927

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

IPC: G06F1300

CPC classification number: G06F12/0831

Abstract: In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.

Abstract translation: 响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。 组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。 总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。 一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。 在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。 否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

公开(公告)号：US06502171B1

公开(公告)日：2002-12-31

申请号：US09368231

申请日：1999-08-04

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F12/0831 ,  G06F12/0811

Abstract: In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.

Abstract translation: 组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务 或目标数据。 具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。 取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

公开(公告)号：US06502168B1

公开(公告)日：2002-12-31

申请号：US09404028

申请日：1999-09-23

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F11/349 ,  G06F12/0831 ,  G06F2201/885

Abstract: According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.

Abstract translation: 根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。 指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。 响应于接收到高速缓存操作请求，确定是否更新状态指示。 响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。 状态指示随后被写回缓存目录。 因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。