公开(公告)号：US20100262720A1

公开(公告)日：2010-10-14

申请号：US12420889

申请日：2009-04-09

申请人： George William Daly, JR. ,  Guy Lynn Guthrie ,  Ross Boyd Leavens ,  Joseph Gerald McDonald ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

发明人： George William Daly, JR. ,  Guy Lynn Guthrie ,  Ross Boyd Leavens ,  Joseph Gerald McDonald ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F3/00

CPC分类号： G06F13/4022

摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.

摘要翻译： 用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。 在这种情况下，通道标识符表示属于I / O流的I / O命令。 命令位置指示符分配给每个I / O命令。 命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。 当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

公开(公告)号：US07480772B2

公开(公告)日：2009-01-20

申请号：US11835984

申请日：2007-08-08

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US07454737B2

公开(公告)日：2008-11-18

申请号：US11552306

申请日：2006-10-24

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50 ,  H03K17/693

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。

公开(公告)号：US20080249758A1

公开(公告)日：2008-10-09

申请号：US12106416

申请日：2008-04-21

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

公开(公告)号：US20080178159A1

公开(公告)日：2008-07-24

申请号：US12057829

申请日：2008-03-28

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F9/455

CPC分类号： G06F11/3664 ,  G06F11/3636

摘要： The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.

摘要翻译： 被测系统中感兴趣的信号在被测系统的多个操作周期中的每一个期间的信号状态被存储在跟踪文件中。 与信号状态相关联，还存储关于在多个周期中的特定周期期间由控制程序请求的访问信号状态的信息。 从跟踪文件中产生一个演示文稿，对于至少在被测系统内感兴趣的信号，呈现多个信号状态指示，每个信号状态指示各自表示信号在多个操作周期之一中具有的状态 的被测系统。 演示文稿还以图形上独特的方式指示至少一个操作周期，在该周期期间控制程序请求访问信号的状态，使得控制程序对被测系统的状态的影响在视觉上是明显的 。

公开(公告)号：US07392501B2

公开(公告)日：2008-06-24

申请号：US11408583

申请日：2006-04-21

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F15/177

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

摘要翻译： 公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。 根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。 此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。

公开(公告)号：US07392169B2

公开(公告)日：2008-06-24

申请号：US10970469

申请日：2004-10-21

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

公开(公告)号：US20080140953A1

公开(公告)日：2008-06-12

申请号：US12033454

申请日：2008-02-19

申请人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US07366999B2

公开(公告)日：2008-04-29

申请号：US11408835

申请日：2006-04-21

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

公开(公告)号：US07197604B2

公开(公告)日：2007-03-27

申请号：US10965151

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。