公开(公告)号：US06836855B2

公开(公告)日：2004-12-28

申请号：US10388076

申请日：2003-03-13

申请人： Richard Louis Arndt

发明人： Richard Louis Arndt

IPC分类号： G06F1100

CPC分类号： G06F11/0793 ,  G01B21/20 ,  G06F11/0712 ,  G06F11/0787 ,  G06F11/1438

摘要： A method, system, and apparatus for isolating fatal data fetch errors to a single partition within a logically partitioned data processing system. In one embodiment, the logically partitioned data processing system includes a plurality of operating systems and a plurality of processors is provided. Each of the operating systems is assigned to a separate one of a plurality of logical partitions. Each of the processors is assigned to one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor for creating and maintaining separation of the plurality of logical partitions. The hypervisor contains services and functions accessed by each of the logical partitions and, to prevent fatal data fetch errors in one partition from effecting other partitions within the logically partitioned data processing system, the hypervisor includes a plurality of data structure areas. Fatal data fetch errors occurring in one of the plurality of data structure areas results in rebooting data processing system components associated with only a single effected logical partition of the plurality of logical partitions within the logically partitioned data processing system.

摘要翻译： 用于将致命数据提取错误分离到逻辑分区数据处理系统中的单个分区的方法，系统和装置。 在一个实施例中，逻辑分区数据处理系统包括多个操作系统，并且提供多个处理器。 每个操作系统被分配给多个逻辑分区中的单独一个。 每个处理器被分配给多个逻辑分区中的一个。 逻辑分区数据处理系统还包括用于创建和维护多个逻辑分区的分离的管理程序。 管理程序包含由每个逻辑分区访问的服务和功能，并且为了防止一个分区中的致命数据获取错误影响逻辑分区数据处理系统中的其他分区，管理程序包括多个数据结构区域。 在多个数据结构区域之一中发生的致命数据提取错误导致重新启动与逻辑分区数据处理系统内的多个逻辑分区的仅一个受影响的逻辑分区相关联的数据处理系统组件。

公开(公告)号：US06751679B1

公开(公告)日：2004-06-15

申请号：US09714732

申请日：2000-11-16

申请人： Richard Louis Arndt ,  Craig Henry Shempert

发明人： Richard Louis Arndt ,  Craig Henry Shempert

IPC分类号： G06F300

CPC分类号： G06F12/1441 ,  G06F21/78 ,  G06F21/85

摘要： A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and maintaining security over the distribution mechanism. In one embodiment, this invention is used by a data processing system including a system processor connected to a plurality of operating system instances that are allocated individual system functions. Using logical partitioning, each operating system instance's access is limited to its own partition. Address buses to system functions are manipulated to make the functions appear at appropriate memory locations expected by the operating system instances. Accordingly, an inverter can be inserted on the address bus to change the address to a given distance in memory safe from operating system accessibility, for example, a page boundary. The functions' control areas are moved to a secure area of memory while the functions are remapped to the normal address ranges expected by the operating system instance in the respective logical partition.

摘要翻译： 通过将多功能芯片中的功能重定位以跨多个逻辑分区分布并保持分布机制的安全性，提供了用于安全可编程寻址的方法，系统和装置。 在一个实施例中，本发明由数据处理系统使用，所述数据处理系统包括连接到被分配单个系统功能的多个操作系统实例的系统处理器。 使用逻辑分区，每个操作系统实例的访问仅限于其自己的分区。 对系统功能的地址总线进行操作，使功能出现在操作系统实例预期的适当的存储位置。 因此，可以将逆变器插入到地址总线上，以将地址改变为在操作系统可访问性（例如页面边界）中的内存中的给定距离。 功能的控制区域被移动到存储器的安全区域，而功能被重新映射到由相应的逻辑分区中的操作系统实例预期的正常地址范围。

公开(公告)号：US06629162B1

公开(公告)日：2003-09-30

申请号：US09589665

申请日：2000-06-08

申请人： Richard Louis Arndt ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Steven Mark Thurber

IPC分类号： G06F1328

CPC分类号： G06F13/28

摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned system, from accessing data from a memory location allocated to another OS image is provided. The system includes logical partitions, operating systems (OSs), memory locations, I/O adapters (IOAs), and a hypervisor. Each operating system image is assigned memory locations and input/output adapter is assigned to a logical partition. Each of the input/output adapters is assigned a range of I/O bus DMA addresses by the hypervisor. When a DMA operation request is received from an OS image, the hypervisor checks that the memory address range and the I/O adapter are allocated to the requesting OS image and that the I/O bus DMA range is within the that allocated to the I/O adapter. If these checks are passed, the hypervisor performs the requested mapping; otherwise the request is rejected.

摘要翻译： 提供一种用于防止在逻辑分区系统中由操作系统（OS）映像使用的输入/输出（I / O）适配器访问分配给另一个OS映像的存储器位置的数据的方法，系统和装置。 该系统包括逻辑分区，操作系统（OS），内存位置，I / O适配器（IOA）和管理程序。 分配每个操作系统映像的内存位置，并将分配给输入/输出适配器。 每个输入/输出适配器由管理程序分配一系列I / O总线DMA地址。 当从OS映像接收到DMA操作请求时，管理程序检查存储器地址范围和I / O适配器是否被分配给请求的OS映像，并且I / O总线DMA范围在分配给I / O适配器。 如果这些检查通过，管理程序将执行所请求的映射; 否则请求被拒绝。

公开(公告)号：US06430643B1

公开(公告)日：2002-08-06

申请号：US09389438

申请日：1999-09-02

申请人： Richard Louis Arndt

发明人： Richard Louis Arndt

IPC分类号： G06F1326

CPC分类号： G06F13/26 ,  G06F2213/2412 ,  G06F2213/2418

摘要： An interrupt handling mechanism within a data processing system is used to assign interrupts among multiple interrupt presentation controllers while avoiding the use of a significant amount of signal lines. An interrupt input message from an interrupt source controller is input into an interrupt presentation controller. Fields are added to the interrupt input message to facilitate the assignment of the interrupt input message to an interrupt presentation controller. The input interrupt message is passed between the interrupt presentation controller in a sequential fashion such that the collection of controllers forms a logical ring. On the first circle of the ring, the priority of the processors capable of handling the interrupt is discovered. A second pass through the interrupt presentation controller is used to assign the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as to best priority. The condition in which no acceptable processors are found for servicing the interrupt request is provided for by rejecting the interrupt.

摘要翻译： 数据处理系统中的中断处理机制用于在多个中断呈现控制器之间分配中断，同时避免使用大量的信号线。 来自中断源控制器的中断输入消息被输入到中断呈现控制器中。 字段被添加到中断输入消息，以便于将中断输入消息分配给中断呈现控制器。 输入中断消息以顺序方式在中断呈现控制器之间传递，使得控制器的集合形成逻辑环。 在环的第一圈，发现能处理中断的处理器的优先级。 通过中断呈现控制器的第二次通过用于分配能够进行中断的第一处理器，并且具有与第一次通过中所指出的优先级相同或更低的优先级。 通过拒绝中断来提供不能接受处理器用于维护中断请求的条件。

公开(公告)号：US5802378A

公开(公告)日：1998-09-01

申请号：US675427

申请日：1996-06-26

申请人： Richard Louis Arndt ,  Frank Eliot Levine ,  Edward John Silha ,  Edward Hugh Welbon

发明人： Richard Louis Arndt ,  Frank Eliot Levine ,  Edward John Silha ,  Edward Hugh Welbon

IPC分类号： G06F9/48 ,  G06F9/46 ,  G06F11/30 ,  G06F11/34 ,  G06F15/78 ,  G06F7/00

CPC分类号： G06F11/3495

摘要： The present invention provides a system and method which ensures that machine state data, for each CPU in an MP system, corresponding to a specific point in time will always be saved, regardless of whether the system interrupt handler is enabled or disabled. A series of special purpose registers (SPR) are included, which are associated with the performance monitoring mechanism in each processor in the MP system. A time base mechanism in each CPU is used and synchronized across the entire MP system. When the time base mechanism requests that the machine state be recorded, the performance monitor then immediately stores the machine state values in the special purpose registers. Thus, the state of the each CPU in the MP system is saved at the identical point in time. The performance monitor issues an interrupt request to the interrupt handler and, if interrupts are enabled, the machine state data is stored for post-processing, or the like. However, if the interrupt handler has disabled interrupts, then the machine state data remains in the SPRs until interrupts are enabled and the data (corresponding to the same point in time) is then read from the special purpose registers into memory, or the like, for post-processing.

摘要翻译： 本发明提供一种系统和方法，其确保对于MP系统中的每个CPU对应于特定时间点的机器状态数据将始终被保存，而不管系统中断处理程序是启用还是禁用。 包括一系列专用寄存器（SPR），与MP系统中每个处理器的性能监视机制相关联。 每个CPU中的时基机制在整个MP系统中被使用和同步。 当时基机制请求记录机器状态时，性能监视器立即将机器状态值存储在专用寄存器中。 因此，MP系统中的每个CPU的状态保存在相同的时间点。 性能监视器向中断处理程序发出中断请求，并且如果允许中断，则存储机器状态数据用于后处理等。 然而，如果中断处理程序禁止中断，则机器状态数据保留在SPR中，直到中断被使能，然后将数据（对应于同一时间点）从专用寄存器读取到存储器等中， 用于后期处理。