公开(公告)号：US08782024B2

公开(公告)日：2014-07-15

申请号：US10777724

申请日：2004-02-12

申请人： Richard Louis Arndt ,  Bruce G. Mealey ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Bruce G. Mealey ,  Steven Mark Thurber

IPC分类号： G06F7/00

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F9/5077

摘要： A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.

摘要翻译： 提供了一种用于在逻辑分区数据处理系统中的逻辑分区之间共享资源并且以这样的方式管理对资源的改变的机制，使得共享操作系统能够以优雅的方式处理各种转换。 四个管理程序功能加上特定的返回代码管理一个分区所拥有的资源到另一个（客户端）分区的授权，客户端分区接受授予的资源，客户机分区返回授权资源，以及由所拥有的分区撤销访问 。 这四个虚拟机管理程序功能由拥有和客户机分区明确地调用，或者由管理程序自动地响应于分区终止而调用。 管理程序功能提供所需的基础设施来管理分区之间逻辑资源的共享。

公开(公告)号：US08213294B2

公开(公告)日：2012-07-03

申请号：US11426592

申请日：2006-06-27

申请人： Richard Louis Arndt ,  Thomas Schlipf ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Thomas Schlipf ,  Steven Mark Thurber

IPC分类号： G01R31/08

CPC分类号： H04L47/10 ,  H04L41/0659 ,  H04L47/11 ,  H04L47/30 ,  H04L47/32 ,  H04L47/39 ,  H04L49/90

摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.

摘要翻译： 用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。 在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。 队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。 然后恢复根组合对队列的访问。

公开(公告)号：US07734842B2

公开(公告)日：2010-06-08

申请号：US11390790

申请日：2006-03-28

申请人： Richard Louis Arndt ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Steven Mark Thurber

IPC分类号： G06F13/28 ,  G06F12/08

CPC分类号： G06F11/141 ,  G06F12/08 ,  G06F12/1081

摘要： A computer-implemented method, apparatus, and computer program product are disclosed for managing direct memory access (DMA) write page faults using a pool of substitute pages. A computer system platform resolves a DMA write page fault for a page that is dedicated to an Input/Output (I/O) adapter. The I/O adapter attempts to write DMA data to the page. A determination is made that the page is unavailable for writing. The DMA data is then written to data locations in a substitute page that was selected from the pool of substitute pages. A flag is then set in a flag location for each one of the data locations. The flag locations correspond to the data locations. When a flag is set, the flag indicates that DMA write data is present in the data location that corresponds to that flag's flag location.

摘要翻译： 公开了一种计算机实现的方法，装置和计算机程序产品，用于使用替代页面池来管理直接存储器访问（DMA）写页错误。 计算机系统平台解决专用于输入/输出（I / O）适配器的页面的DMA写入页错误。 I / O适配器尝试将DMA数据写入页面。 确定页面无法写入。 然后将DMA数据写入从替代页面池中选择的替代页面中的数据位置。 然后将标志设置在每个数据位置的标志位置。 标志位置对应于数据位置。 当标志置位时，标志表示DMA数据存在于该标志位置对应的数据位置。

公开(公告)号：US07398427B2

公开(公告)日：2008-07-08

申请号：US10887524

申请日：2004-07-08

申请人： Richard Louis Arndt ,  Patrick Allen Buckland ,  Gregory Michael Nordstrom ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Patrick Allen Buckland ,  Gregory Michael Nordstrom ,  Steven Mark Thurber

IPC分类号： G06F11/00

CPC分类号： G06F11/2736

摘要： Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

摘要翻译： 用于在数据处理系统中隔离输入/输出适配器错误域的方法，装置和系统。 在一个输入/输出适配器中发生的错误与数据处理系统的其他输入/输出适配器隔离，主机桥中的功能将输入/输出适配器连接到数据处理系统的系统总线，从而允许使用低 成本，行业标准交换机和主桥外部的桥梁。

公开(公告)号：US20070297434A1

公开(公告)日：2007-12-27

申请号：US11426592

申请日：2006-06-27

申请人： Richard Louis Arndt ,  Thomas Schlipf ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Thomas Schlipf ,  Steven Mark Thurber

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L41/0659 ,  H04L47/11 ,  H04L47/30 ,  H04L47/32 ,  H04L47/39 ,  H04L49/90

摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.

摘要翻译： 用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。 在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。 队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。 然后恢复根组合对队列的访问。

公开(公告)号：US06523140B1

公开(公告)日：2003-02-18

申请号：US09414337

申请日：1999-10-07

申请人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： H02H305

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/0793

摘要： A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.

摘要翻译： 提供了一种方法和实现的计算机系统，其中在信息传输交易期间检测到故障状况时获取特定的设备识别信息，并且将该条件报告给所识别的设备的设备驱动程序以进行纠正，而不启动系统关闭， 下。 在一个示例中，捕获PCI适配器序列信息，包括标签号，请求者总线号，请求者设备号和请求者功能号，并用于报告错误状况，以便在恢复操作中识别和隔离适配器。

公开(公告)号：US07266631B2

公开(公告)日：2007-09-04

申请号：US10902611

申请日：2004-07-29

申请人： Richard Louis Arndt ,  Patrick Allen Buckland ,  Gregory Michael Nordstrom ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Patrick Allen Buckland ,  Gregory Michael Nordstrom ,  Steven Mark Thurber

IPC分类号： G06F13/20 ,  G06F13/36 ,  G06F13/40 ,  G06F13/10

CPC分类号： G06F13/126

摘要： Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.

摘要翻译： 用于控制数据处理系统中的输入/输出适配器数据流操作的方法，装置和系统，该数据处理系统包括结合虚拟信道资源的业务类机制中的至少一个，以便能够将加载/存储和DMA流关联到/ 以及用于将放松的排序位与加载/存储操作相关联的输入/输出适配器的放松排序机制。 用于控制输入/输出适配器数据流的功能在将输入/输出适配器连接到数据处理系统的系统总线的主机桥中提供。

公开(公告)号：US06823404B2

公开(公告)日：2004-11-23

申请号：US09766764

申请日：2001-01-23

申请人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F300

CPC分类号： G06F13/28

摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.

摘要翻译： 用于防止在逻辑分区的数据处理系统中由操作系统（OS）映像使用的输入/输出（I / O）适配器的方法，系统和装置从分配给另一个OS映像的存储器位置获取或破坏数据 在数据处理系统内提供。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间通过分配每个输入/输出适配器一个I / O范围的逻辑分区之一和分配给其他逻辑分区的存储器位置之间的输入/输出适配器之间的数据传输 总线DMA地址。 I / O适配器（IOA）通过终端桥连接到PCI主机桥。 单个终端桥可以支持多个IOA，在这种情况下，每个终端桥具有多组范围寄存器，每个范围寄存器与其所连接的IOA中的相应一个相关联。 提供了一个仲裁器，其选择一个输入/输出适配器来使用PCI总线。 终端桥可以检查从仲裁器到IOA的授权信号，以确定要使用哪个范围寄存器组。

公开(公告)号：US06643727B1

公开(公告)日：2003-11-04

申请号：US09589664

申请日：2000-06-08

申请人： Richard Louis Arndt ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Steven Mark Thurber

IPC分类号： G06F1336

CPC分类号： H04L1/00

摘要： A method, system, and apparatus for isolating an input/output (I/O) bus error, received from an I/O adapter, from the other I/O adapters that may be in different partitions within a logically partitioned data process system is provided. In one embodiment, the logically partitioned data processing system includes a system bus, a processing unit, a memory unit, a host bridge, a plurality of terminal bridges, and a plurality of input/output adapters. The processing unit, memory unit, and the host bridge are all coupled to each other through the system bus. Each of the plurality of terminal bridges is coupled to the host bridge through a first bus. Each of the input/output adapters is coupled to one of the plurality of terminal bridges through a one of a plurality of second buses, such that each input/output adapter corresponds to a single terminal bridge. Each of the input/output adapters are assigned to one of a plurality of logical partitions within the data processing system. Each of the terminal bridges isolates errors received from a respective one of the input/output adapters from other input/output adapters, some of which may be within a different one of the plurality of logical partitions.

摘要翻译： 用于将从I / O适配器接收的输入/输出（I / O）总线错误与可能在逻辑分区数据处理系统中的不同分区中的其他I / O适配器隔离的方法，系统和装置是 提供。 在一个实施例中，逻辑分区数据处理系统包括系统总线，处理单元，存储单元，主桥，多个终端桥以及多个输入/输出适配器。 处理单元，存储单元和主桥都通过系统总线相互耦合。 多个终端桥中的每一个通过第一总线耦合到主桥。 每个输入/输出适配器通过多个第二总线中的一个耦合到多个终端桥中的一个，使得每个输入/输出适配器对应于单个终端桥。 每个输入/输出适配器被分配给数据处理系统内的多个逻辑分区中的一个。 每个终端桥将从相应的一个输入/输出适配器接收的错误与其他输入/输出适配器隔离，其中一些输入/输出适配器中的一些可能在多个逻辑分区中的不同的一个之内。

公开(公告)号：US5701495A

公开(公告)日：1997-12-23

申请号：US573918

申请日：1995-12-18

申请人： Richard Louis Arndt ,  James Otto Nicholson ,  Edward John Silha ,  Steven Mark Thurber ,  Amy May Youngs

发明人： Richard Louis Arndt ,  James Otto Nicholson ,  Edward John Silha ,  Steven Mark Thurber ,  Amy May Youngs

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177

CPC分类号： G06F9/4812

摘要： An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

摘要翻译： 数据处理系统中的中断子系统可从低端单处理器系统扩展到高端多处理器（MP）系统。 该中断子系统提供了来自多个源的中断排队，以及用于将中断排队到多处理器系统中的最佳处理器。 外部中断机制分为两层，一个中断路由层和一个中断表示层。 中断路由层将中断条件路由到中断表示层中的中断管理区域的适当实例。 中断表示层将中断源传送到服务/处理中断的系统软件。 通过在中断子系统内提供两层，可以写入独立于中断类型或来源的应用程序或系统软件。 中断路由层从软件隐藏了特定硬件实现的细节。 中断演示层与系统和/或应用软件接口，并提供独立于硬件的功能。