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    SCAN RESPONSE REUSE METHOD AND APPARATUS
    92.
    发明申请
    SCAN RESPONSE REUSE METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20160216328A1

    公开(公告)日：2016-07-28

    申请号：US15089978

    申请日：2016-04-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

    CORE CIRCUIT TEST ARCHITECTURE
    93.
    发明申请
    CORE CIRCUIT TEST ARCHITECTURE 审中-公开
    核心电路测试架构

    公开(公告)号：US20160209471A1

    公开(公告)日：2016-07-21

    申请号：US15086624

    申请日：2016-03-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/28

    CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

    Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

    Abstract translation: 集成电路包括具有触发器的组合逻辑，具有用于接收要应用于组合逻辑的测试激励数据的扫描输入的并行扫描路径，与组合逻辑的组合连接，用于将刺激数据应用于组合逻辑并从 组合逻辑，用于发送从组合逻辑获得的测试响应数据的扫描输出以及具有用于操作并行扫描路径的使能输入和选择输入的控制输入，每个扫描路径包括组合逻辑的触发器， 测试模式串联连接，比较电路表示接收到的测试响应数据与故障标志输出的期望数据的比较结果，其中一个扫描路径包括具有耦合到故障的输入的扫描单元 标志输出。

    TSVs connected to ground and combined stimulus and testing leads
    95.
    发明授权
    TSVs connected to ground and combined stimulus and testing leads 有权
    连接到地面的TSV和组合的刺激和测试线索

    公开(公告)号：US09383403B2

    公开(公告)日：2016-07-05

    申请号：US13785284

    申请日：2013-03-05

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Baher S. Haroun

    IPC: G01R31/26 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

    Abstract translation: 本公开描述了一种用于测试半导体器件内的TSV的新颖方法和装置。 根据本公开中所示和描述的实施例，可以通过刺激和测量来自TSV的第一端的响应来测试TSV，同时TSV的第二端保持在地电位。 根据本公开，可以并行测试半导体器件内的多个TSV以减少TSV测试时间。

    IC and core taps with input and linking module circuitry
    97.
    发明授权
    IC and core taps with input and linking module circuitry 有权
    IC和核心抽头与输入和链接模块电路

    公开(公告)号：US09347992B2

    公开(公告)日：2016-05-24

    申请号：US14728580

    申请日：2015-06-02

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

    Enable and select inputs operate combinational logic parallel scan paths
    99.
    发明授权
    Enable and select inputs operate combinational logic parallel scan paths 有权
    启用和选择输入操作组合逻辑并行扫描路径

    公开(公告)号：US09329230B2

    公开(公告)日：2016-05-03

    申请号：US14707794

    申请日：2015-05-08

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/28 ,  G01R31/3177 ,  G06F11/25 ,  G01R31/3185 ,  G01R31/3173

    CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

    Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

    Abstract translation: 集成电路包括具有触发器的组合逻辑，具有用于接收要应用于组合逻辑的测试激励数据的扫描输入的并行扫描路径，与组合逻辑的组合连接，用于将刺激数据应用于组合逻辑并从 组合逻辑，用于发送从组合逻辑获得的测试响应数据的扫描输出以及具有用于操作并行扫描路径的使能输入和选择输入的控制输入，每个扫描路径包括组合逻辑的触发器， 测试模式串联连接，比较电路表示接收到的测试响应数据与故障标志输出的期望数据的比较结果，其中一个扫描路径包括具有耦合到故障的输入的扫描单元 标志输出。

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