公开(公告)号：US11995806B2

公开(公告)日：2024-05-28

申请号：US17080884

申请日：2020-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram Vijayanbabu Appia ,  Sujith Shivalingappa

IPC: G06T5/80 ,  G06T3/047 ,  G06T3/18

CPC classification number: G06T5/80 ,  G06T3/047 ,  G06T3/18 ,  G06T2200/32 ,  G06T2207/10024 ,  G06T2207/20021

Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.

公开(公告)号：US11974062B2

公开(公告)日：2024-04-30

申请号：US17690829

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Brijesh Jadav ,  Gang Hua ,  Niraj Nandan ,  Rajasekhar Reddy Allu ,  Ankur Ankur ,  Mayank Mangla

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US20240040096A1

公开(公告)日：2024-02-01

申请号：US17983905

申请日：2022-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing-Fei Ren ,  Hrushikesh Garud ,  Rajasekhar Allu ,  Gang Hua ,  Niraj Nandan ,  Mayank Mangla ,  Mihir Narendra Mody

IPC: H04N9/64 ,  G06T7/90 ,  G06T7/00

CPC classification number: H04N9/646 ,  G06T7/90 ,  G06T7/0002 ,  G06T2207/10024 ,  G06T2207/30168

Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.

公开(公告)号：US20230388661A1

公开(公告)日：2023-11-30

申请号：US18194249

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Manoj Koul ,  Pandy Kalimuthu ,  David Stoller

IPC: H04N23/81 ,  H04N23/84 ,  H04N23/88

CPC classification number: H04N23/81 ,  H04N23/843 ,  H04N23/88

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

公开(公告)号：US20230385102A1

公开(公告)日：2023-11-30

申请号：US18175364

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Pandy Kalimuthu

IPC: G06F9/48 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/30189 ,  G06F9/30079

Abstract: Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.

公开(公告)号：US20230350819A1

公开(公告)日：2023-11-02

申请号：US18345098

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US11770624B2

公开(公告)日：2023-09-26

申请号：US18072813

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Rajasekhar Allu ,  Niraj Nandan

IPC: H04N5/235 ,  H04N9/04 ,  H04N1/60 ,  H04N23/84 ,  G06T1/20 ,  H04N9/67

CPC classification number: H04N23/843 ,  G06T1/20 ,  H04N9/67 ,  H04N2209/046

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US20230239585A1

公开(公告)日：2023-07-27

申请号：US18194762

申请日：2023-04-03

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Shashank Dabral ,  Mihir Narendra Mody ,  Rajasekhar Reddy Allu ,  Niraj Nandan

IPC: G06T9/00 ,  H04N9/78

CPC classification number: H04N23/88 ,  H04N9/78 ,  H04N23/71 ,  H04N23/76 ,  H04N23/741

Abstract: Local automatic white balance (AWB) of wide dynamic range (WDR) images is provided. Methods and systems include collecting, by an image signal processor (ISP), statistics for local AWB from at least one wide dynamic range (WDR) image received by the ISP; generating, by a processor, based on the statistics, local gain lookup tables (LUTs), one for each color channel represented in the WDR image(s), each local gain LUT providing a correlation between gain and intensity; and storing the local gain LUTs. Further processing includes, for each of multiple pixels of a WDR image to be output calculating an intensity value, accessing the local gain LUT for the color channel corresponding to that pixel using the calculated intensity value to identify a corresponding local gain value, and applying the local gain value to that pixel.

公开(公告)号：US11693795B2

公开(公告)日：2023-07-04

申请号：US17138740

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US11630701B2

公开(公告)日：2023-04-18

申请号：US16377966

申请日：2019-04-08

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F13/14 ,  G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06T1/20 ,  G06F5/12 ,  G06F13/16 ,  G06F15/78 ,  G06F13/28 ,  G06F13/40 ,  G06F11/07

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.