公开(公告)号：US20230385114A1

公开(公告)日：2023-11-30

申请号：US18175333

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Niraj Nandan ,  Rajasekhar Allu ,  Ankur Ankur

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06F9/544

Abstract: A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.

公开(公告)号：US20240221133A1

公开(公告)日：2024-07-04

申请号：US18148244

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Rajasekhar Allu ,  Mihir Narenda Mody ,  Ankur Ankur ,  Pandy Kalimuthu

IPC: G06T5/00 ,  G06T1/60

CPC classification number: G06T5/006 ,  G06T1/60

Abstract: Various embodiments disclosed herein relate to distorted pixel correction, and more specifically to producing an output image using variable-sized groupings of lines of pixels of an input image. An example embodiment includes a method of using variable-sized pixel groupings when processing distorted image data. The method comprises identifying a context of an image captured by an imaging system, wherein the image comprises lines of pixels that form a distorted representation of a scene, identifying, based on the context of the image, a mapping of variable-sized groupings of the lines to memory ranges in a buffer, wherein an image processing subsystem produces block rows of an output image based on the mapping, and wherein a size of each of the variable-sized groupings varies based on how many of the lines the image processing subsystem uses to produce each of the block rows, and supplying the mapping to the image processing subsystem.

公开(公告)号：US11974062B2

公开(公告)日：2024-04-30

申请号：US17690829

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Brijesh Jadav ,  Gang Hua ,  Niraj Nandan ,  Rajasekhar Reddy Allu ,  Ankur Ankur ,  Mayank Mangla

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US12125122B2

公开(公告)日：2024-10-22

申请号：US17556161

申请日：2021-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Ankur Ankur ,  Mayank Mangla ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06T1/20 ,  G06F9/48 ,  G06F11/10 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4812 ,  G06F11/1004 ,  G06T1/60

Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.

公开(公告)号：US12111780B2

公开(公告)日：2024-10-08

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Ankur Ankur ,  Vivek Vilas Dhande ,  Kedar Satish Chitnis ,  Niraj Nandan ,  Brijesh Jadav ,  Shyam Jagannathan ,  Prithvi Shankar Yeyyadi Anantha ,  Santhanakrishnan Narayanan Narayanan

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.