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公开(公告)号：US12244937B2
公开(公告)日：2025-03-04
申请号：US18309055
申请日：2023-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Pandy Kalimuthu
IPC: H04N23/85 , H04N23/11 , H04N23/84 , H04N25/13 , H04N25/131
Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.
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2.发明公开公开(公告)号：US20240221133A1
公开(公告)日：2024-07-04
申请号：US18148244
申请日：2022-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Niraj Nandan , Rajasekhar Allu , Mihir Narenda Mody , Ankur Ankur , Pandy Kalimuthu
Abstract: Various embodiments disclosed herein relate to distorted pixel correction, and more specifically to producing an output image using variable-sized groupings of lines of pixels of an input image. An example embodiment includes a method of using variable-sized pixel groupings when processing distorted image data. The method comprises identifying a context of an image captured by an imaging system, wherein the image comprises lines of pixels that form a distorted representation of a scene, identifying, based on the context of the image, a mapping of variable-sized groupings of the lines to memory ranges in a buffer, wherein an image processing subsystem produces block rows of an output image based on the mapping, and wherein a size of each of the variable-sized groupings varies based on how many of the lines the image processing subsystem uses to produce each of the block rows, and supplying the mapping to the image processing subsystem.
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公开(公告)号：US20230388661A1
公开(公告)日：2023-11-30
申请号：US18194249
申请日：2023-03-31
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Manoj Koul , Pandy Kalimuthu , David Stoller
CPC classification number: H04N23/81 , H04N23/843 , H04N23/88
Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.
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公开(公告)号：US20230385102A1
公开(公告)日：2023-11-30
申请号：US18175364
申请日：2023-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Pandy Kalimuthu
CPC classification number: G06F9/4881 , G06F9/30189 , G06F9/30079
Abstract: Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.
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公开(公告)号：US20240040266A1
公开(公告)日：2024-02-01
申请号：US18147964
申请日：2022-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Jing-Fei Ren , Mayank Mangla , Niraj Nandan , Mihir Mody , Pandy Kalimuthu
CPC classification number: H04N23/76 , H04N23/11 , H04N23/843 , H04N23/81 , H04N23/667
Abstract: A system is provided. The system generally includes a first processor configured to receive image input data from a red-green-blue infrared (RGBIR) sensor. The first processor of the system is configured to generate a first intermediate image data from the image input data. The system generally includes a second processor. The second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (RGB) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (IR) image data from the first intermediate image data. The system generally includes a third processor. The third processor of the system is configured to process the third intermediate image data. The system generally includes a fourth processor. The fourth processor of the system is configured to process the second image data.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11743612B2
公开(公告)日：2023-08-29
申请号：US17555145
申请日：2021-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gang Hua , Rajasekhar Reddy Allu , Mihir Narendra Mody , Niraj Nandan , Mayank Mangla , Pandy Kalimuthu
IPC: H04N25/611 , G06T3/40 , G06T1/60 , H04N25/13
CPC classification number: H04N25/611 , G06T1/60 , G06T3/4015 , H04N25/13
Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules. In some embodiments, an in-pipeline CAC design is used that: is configured to perform on-the-fly CAC without any out-of-pipeline memory traffic; enables use of wide dynamic range (WDR) sensors; uses bicubic interpolation; supports vertical and horizontal chromatic aberration red/blue color channel offsets, reduces CAC line memory requirements, and supports flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.
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公开(公告)号：US12207002B2
公开(公告)日：2025-01-21
申请号：US18194249
申请日：2023-03-31
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Manoj Koul , Pandy Kalimuthu , David Stoller
Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.
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8.发明授权公开(公告)号：US12192653B2
公开(公告)日：2025-01-07
申请号：US18343018
申请日：2023-06-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gang Hua , Rajasekhar Reddy Allu , Mihir Narendra Mody , Niraj Nandan , Mayank Mangla , Pandy Kalimuthu
IPC: H04N25/611 , G06T1/60 , G06T3/4015 , H04N25/13
Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components. An in-pipeline CAC design may be used to perform on-the-fly CAC without any out-of-pipeline memory traffic; enable use of wide dynamic range (WDR) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce CAC line memory requirements, and support flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.
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公开(公告)号：US11927629B2
公开(公告)日：2024-03-12
申请号：US17486675
申请日：2021-09-27
Applicant: Texas Instruments Incorporated
Inventor： Pandy Kalimuthu , Anthony Joseph Lell
IPC: G01R31/3177 , G06F1/10
CPC classification number: G01R31/3177 , G06F1/10
Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.
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公开(公告)号：US20240040268A1
公开(公告)日：2024-02-01
申请号：US18309055
申请日：2023-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Pandy Kalimuthu
CPC classification number: H04N23/85 , H04N23/843 , H04N23/11 , H04N25/131
Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.
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